Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 74 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 43. Enhanced Parallel Peripheral Interface—External Clock
V
DD_EXT
1.8 V Nominal
V
DD_EXT
3.3 V Nominal
Parameter Min Max Min Max Unit
Timing Requirements
t
PCLKW
EPPI_CLK Width for Data Transmit, FS External
Data/FS Receive
1
[0.5 × t
SCLK0
– 0.5] or [5.5] [0.5 × t
SCLK0
– 0.5] or [5.5] ns
EPPI_CLK Width for Data Transmit, FS Internal
Data/FS Transmit
1
[0.5 × t
SCLK0
– 1] or [7.5] [0.5 × t
SCLK0
– 1] or [7.5] ns
t
PCLK
EPPI_CLK Period for Data Receive, FS External
Data/FS Receive
1
[t
SCLK0
– 1] or [12] [t
SCLK0
– 1] or [12] ns
EPPI_CLK Period for Data Receive, FS Internal
Data/FS Transmit
1
[t
SCLK0
– 1] or [17] [t
SCLK0
– 1] or [17] ns
t
SFSPE
External Frame Sync Setup Before EPPI_CLK 2 2 ns
t
HFSPE
External Frame Sync Hold After EPPI_CLK 3.7 3.7 ns
t
SDRPE
Receive Data Setup Before EPPI_CLK 2 2 ns
t
HDRPE
Receive Data Hold After EPPI_CLK 3.7 3.7 ns
Switching Characteristics
t
DFSPE
Internal Frame Sync Delay After EPPI_CLK 20.1 15.3 ns
t
HOFSPE
Internal Frame Sync Hold After EPPI_CLK 2.4 2.4 ns
t
DDTPE
Transmit Data Delay After EPPI_CLK 20.1 15.3 ns
t
HDTPE
Transmit Data Hold After EPPI_CLK 2.4 2.4 ns
1
Whichever is greater.
Figure 27. PPI GP Receive Mode with External Frame Sync Timing
Figure 28. PPI GP Transmit Mode with External Frame Sync Timing
t
PCLK
t
SFSPE
DATA SAMPLED /
FRAME SYNC SAMPLED
DATA SAMPLED /
FRAME SYNC SAMPLED
EPPI_D00
-
23
EPPI_CLK
EPPI_FS1/2
t
HFSPE
t
HDRPE
t
SDRPE
t
PCLKW
t
HDTPE
t
SFSPE
DATA DRIVEN /
FRAME SYNC SAMPLED
t
HFSPE
t
DDTPE
t
PCLK
t
PCLKW
EPPI_D00
-
23
EPPI_CLK
EPPI_FS1/2