Datasheet

Rev. 0 | Page 71 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Mobile DDR SDRAM Write Cycle Timing
Table 41. Mobile DDR SDRAM Write Cycle Timing, V
DD_DMC
Nominal 1.8 V
200 MHz
Parameter Min Max Unit
Switching Characteristics
t
DQSS
1
1
Write command to first DMC0_DQS delay = WL × t
CK
+ t
DQSS
.
DMC0_DQS Latching Rising Transitions to Associated Clock Edges 0.75 1.25 t
CK
t
DS
Last Data Valid to DMC0_DQS Delay (Slew > 1 V/ns) 0.48 ns
t
DH
DMC0_DQS to First Data Invalid Delay (Slew > 1 V/ns) 0.48 ns
t
DSS
DMC0_DQS Falling Edge to Clock Setup Time 0.2 t
CK
t
DSH
DMC0_DQS Falling Edge Hold Time From DMC0_CK 0.2 t
CK
t
DQSH
DMC0_DQS Input High Pulse Width 0.4 t
CK
t
DQSL
DMC0_DQS Input Low Pulse Width 0.4 t
CK
t
WPRE
Write Preamble 0.25 t
CK
t
WPST
Write Postamble 0.4 t
CK
t
IPW
Address and Control Output Pulse Width 2.3 ns
t
DIPW
DMC0_DQ and DMC0_DM Output Pulse Width 1.8 ns
Figure 24. Mobile DDR SDRAM Controller Output AC Timing
DMC0_CK
DMC0_DQS0
- 1
DMC0_DQ0 - 15/
DMC0_DQM0 - 1
t
DQSS
t
DSH
t
DSS
t
DQSL
t
DQSH
t
WPST
t
WPRE
t
DS
t
DH
t
DIPW
CONTROL
Write CMD
Dn Dn+1 Dn+2 Dn+3
NOTE: CONTROL = DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE.
ADDRESS = DMC0_A00
- 13, AND DMC0_BA0 - 1.
t
DIPW
t
IPW