Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 70 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Mobile DDR SDRAM Clock and Control Cycle Timing
Mobile DDR SDRAM Read Cycle Timing
Table 39. Mobile DDR SDRAM Read Cycle Timing, V
DD_DMC
Nominal 1.8 V
200 MHz
Parameter Min Max Unit
Switching Characteristics
t
CK
Clock Cycle Time (CL = 2 Not Supported) 5 ns
t
CH
Minimum Clock Pulse Width 0.45 0.55 t
CK
t
CL
Maximum Clock Pulse Width 0.45 0.55 t
CK
t
IS
Control/Address Setup Relative to DMC0_CK Rise 1 ns
t
IH
Control/Address Hold Relative to DMC0_CK Rise 1 ns
Figure 22. Mobile DDR SDRAM Clock and Control Cycle Timing
Table 40. Mobile DDR SDRAM Read Cycle Timing, V
DD_DMC
Nominal 1.8 V
200 MHz
Parameter Min Max Unit
Timing Requirements
t
QH
DMC0_DQ, DMC0_DQS Output Hold Time From DMC0_DQS 1.75 ns
t
DQSQ
DMC0_DQS-DMC0_DQ Skew for DMC0_DQS and Associated
DMC0_DQ Signals
0.4 ns
t
RPRE
Read Preamble 0.9 1.1 t
CK
t
RPST
Read Postamble 0.4 0.6 t
CK
Figure 23. Mobile DDR SDRAM Controller Input AC Timing
NOTE: CONTROL = DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE.
ADDRESS = DMC0_A00
-
13, AND DMC0_BA0
-
1.
DMC0_CK
ADDRESS
CONTROL
t
IS
t
IH
t
CK
t
CH
t
CL
DMC0_CK
DMC0_CK
DMC0_DQS
t
DQSQ
DMC0_DQS
(DATA)
Dn Dn+1 Dn+2 Dn+3
t
RPRE
t
RPST
t
QH