Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 69 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
DDR2 SDRAM Write Cycle Timing
Table 38. DDR2 SDRAM Write Cycle Timing, V
DD_DMC
Nominal 1.8 V
250 MHz
1
1
In order to ensure proper operation of the DDR2, all the DDR2 guidelines have to be strictly followed.
Parameter Min Max Unit
Switching Characteristics
t
DQSS
2
2
Write command to first DMC0_DQS delay = WL × t
CK
+ t
DQSS
.
DMC0_DQS Latching Rising Transitions to Associated Clock Edges –0.15 0.15 t
CK
t
DS
Last Data Valid to DMC0_DQS Delay 0.15 ns
t
DH
DMC0_DQS to First Data Invalid Delay 0.3 ns
t
DSS
DMC0_DQS Falling Edge to Clock Setup Time 0.25 t
CK
t
DSH
DMC0_DQS Falling Edge Hold Time From DMC0_CK 0.25 t
CK
t
DQSH
DMC0_DQS Input High Pulse Width 0.35 t
CK
t
DQSL
DMC0_DQS Input Low Pulse Width 0.35 t
CK
t
WPRE
Write Preamble 0.35 t
CK
t
WPST
Write Postamble 0.4 t
CK
t
IPW
Address and Control Output Pulse Width 0.6 t
CK
t
DIPW
DMC0_DQ and DMC0_DM Output Pulse Width 0.35 t
CK
Figure 21. DDR2 SDRAM Controller Output AC Timing
t
DS
t
DH
t
DQSS
t
DSH
t
DSS
t
WPRE
t
DQSL
t
DQSH
t
WPST
DMC0_LDM
DMC0_CK
DMC0_A00
t
IPW
t
DIPW
DMC0_UDM
DMC0_LDQS
DMC0_UDQS