Datasheet

Rev. 0 | Page 67 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Bus Request/Bus Grant
DDR2 SDRAM Clock and Control Cycle Timing
Table 35. Bus Request/Bus Grant
V
DD_EXT
1.8 V/3.3 V Nominal
Parameter Min Max Unit
Switching Characteristics
t
DBGBR
SMC0_BG Delay After SMC0_BR 2.5 × t
SCLK0
3.5 × t
SCLK0
+ 17.5 ns
t
ENGDAT
DATA Enable After SMC0_BG Deassertion –3 ns
t
DBGDAT
DATA Disable After SMC0_BG Assertion 3 ns
Figure 18. Bus Request/Bus Grant
SMC0_BR
SMC0_BG
t
DBGBR
SMC0 DATA/ADDRESS
CONTROL
t
ENGDAT
t
DNGDAT
Table 36. DDR2 SDRAM Read Cycle Timing, V
DD_DMC
Nominal 1.8 V
250 MHz
Parameter Min Max Unit
Switching Characteristics
t
CK
Clock Cycle Time (CL = 2 Not Supported) 4 ns
t
CH
Minimum Clock Pulse Width 0.45 0.55 t
CK
t
CL
Maximum Clock Pulse Width 0.45 0.55 t
CK
t
IS
Control/Address Setup Relative to DMC0_CK Rise 350 ps
t
IH
Control/Address Hold Relative to DMC0_CK Rise 475 ps
Figure 19. DDR2 SDRAM Clock and Control Cycle Timing
NOTE: CONTROL = DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE.
ADDRESS = DMC0_A00
- 13, AND DMC0_BA0 - 1.
DMC0_CK
ADDRESS
CONTROL
t
IS
t
IH
t
CK
t
CH
t
CL
DMC0_CK