Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 64 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Synchronous Burst Flash Read
Table 31. Synchronous Burst AC Timing (BxMODE = b#11)
V
DD_EXT
1.8 V/3.3 V Nominal
Parameter Min Max Unit
Timing Requirements
t
NDS
DATA-In Setup Before SMC0_NORCLK High 3 ns
t
NDH
DATA-In Hold After SMC0_NORCLK High 1.5 ns
t
NWS
WAIT-In Setup Before SMC0_NORCLK High 3 ns
t
NWH
WAIT-In Hold After SMC0_NORCLK High 1.5 ns
Switching Characteristics
t
NRCLS
NOR_CLK Low Period
1,
2
[0.5 × BCLK × t
SCLK0
– 1] or [7] ns
t
NRCHS
NOR_CLK High Period
1, 2
[0.5 × BCLK × t
SCLK0
– 1] or [7] ns
t
NRCLK
NOR_CLK Period
1, 2
[BCLK × t
SCLK0
– 1] or [15] ns
t
NDO
Output Delay After SMC0_NORCLK High
3
6ns
t
NHO
Output Hold After SMC0_NORCLK High
3
0.8 ns
1
Whichever is greater.
2
BCLKDIV value set using the SMC_BxCTL.BCLK bits. BCLKDIV = (SMC_BxCTL.BCLK + 1).
3
Output = SMC0_Ax (address), SMC0_NORDV, SMC0_ARE, SMC0_AMSx (N0R_CE).
Figure 15. Synchronous Burst AC Interface Timing
t
NDO
t
NWS
t
NWH
t
NDH
t
NDH
t
NDS
t
NDS
t
NHO
Dn Dn+1 Dn+2 Dn+3
SMC0_AMSx
SMC0_NORCLK
SMC0_Ax
(ADDRESS)
SMC0_ARE
NOR_OE
NOTE: SMC0_NORCLK dotted line represents a free running version
of SMC0_NORCLK that is not visible on the SMC0_NORCLK pin.
SMC0_ABE1
-
0
SMC0_Dx
(DATA)
SMC0_NORDV
SMC0_AOE
SMC0_NORWT
t
NDO
t
NDO
t
NDO
t
NDO
t
NDO
t
NDO
t
NDO
t
NHO
t
NRCLS
t
NRCLK
t
NRCHS