Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 62 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Asynchronous Flash Read
Table 29. Asynchronous Flash Read
V
DD_EXT
1.8 V/3.3 V Nominal
Parameter Min Max Unit
Switching Characteristics
t
AMSADV
SMC0_Ax (Address)/SMC0_AMSx Assertion Before SMC0_NORDV
Low
1
PREST × t
SCLK0
– 2 ns
t
WADV
SMC0_NORDV Active Low Width
2
RST × t
SCLK0
– 2 ns
t
DADVARE
SMC0_ARE Low Delay From SMC0_NORDV High
3
PREAT × t
SCLK0
– 2 ns
t
HARE
Output
4
Hold After SMC0_ARE High
5
RHT × t
SCLK0
– 2 ns
t
WARE
6
SMC0_ARE Active Low Width
7
RAT × t
SCLK0
– 2 ns
1
PREST value set using the SMC_BxETIM.PREST bits.
2
RST value set using the SMC_BxTIM.RST bits.
3
PREAT value set using the SMC_BxETIM.PREAT bits.
4
Output signals are SMC0_Ax, SMC0_AMS, SMC0_AOE.
5
RHT value set using the SMC_BxTIM.RHT bits.
6
SMC0_BxCTL.ARDYEN bit = 0.
7
RAT value set using the SMC_BxTIM.RAT bits.
Figure 13. Asynchronous Flash Read
SMC0_Ax
t
AMSADV
t
DADVARE
t
WADV
t
WARE
t
HARE
READ LATCHED
DATA
SMC0_AMSx
(NOR_CE)
SMC0_NORDV
SMC0_ARE
(NOR_OE)
SMC0_Dx
(DATA)