Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 61 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Asynchronous Read
Table 28. Asynchronous Memory Read (BxMODE = b#00)
V
DD_EXT
1.8 V/3.3 V Nominal
Parameter Min Max Unit
Timing Requirements
t
SDATARE
DATA in Setup Before SMC0_ARE High 8.2 ns
t
HDATARE
DATA in Hold After SMC0_ARE High 0 ns
t
DARDYARE
SMC0_ARDY Valid After SMC0_ARE Low
1,
2
(RAT – 2.5) × t
SCLK0
– 17.5 ns
Switching Characteristics
t
ADDRARE
SMC0_Ax/SMC0_AMSx Assertion Before SMC0_
ARE Low
3
(PREST + RST + PREAT) × t
SCLK0
– 2 ns
t
AOEARE
SMC0_AOE Assertion Before SMC0_ARE Low (RST + PREAT) × t
SCLK0
– 2 ns
t
HARE
Output
4
Hold After SMC0_ARE High
5
RHT × t
SCLK0
–2 ns
t
WARE
SMC0_ARE Active Low Width
6
RAT × t
SCLK0
– 2 ns
t
DAREARDY
SMC0_ARE High Delay After SMC0_ARDY
Assertion
1
2.5 × t
SCLK0
3.5 × t
SCLK0
+ 17.5 ns
1
SMC0_BxCTL.ARDYEN bit = 1.
2
RAT value set using the SMC_BxTIM.RAT bits.
3
PREST, RST, and PREAT values set using the SMC_BxETIM.PREST bits, SMC_BxTIM.RST bits, and the SMC_BxETIM.PREAT bits.
4
Output signals are SMC0_Ax, SMC0_AMS, SMC0_AOE, SMC0_ABEx.
5
RHT value set using the SMC_BxTIM.RHT bits.
6
SMC0_BxCTL.ARDYEN bit = 0.
Figure 12. Asynchronous Read
SMC0_ARE
SMC0_AMSx
SMC0_Ax
t
WARE
SMC0_AOE
SMC0_Dx (DATA)
SMC0_ARDY
t
AOEARE
t
ADDRARE
t
DARDYARE
t
HARE
t
HDATARE
t
DAREARDY
t
SDATARE