Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 59 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
TIMING SPECIFICATIONS
Specifications are subject to change without notice.
Clock and Reset Timing
Table 26 and Figure 10 describe clock and reset operations. Per
the CCLK, SYSCLK, SCLK0, SCLK1, DCLK, and OCLK timing
specifications in Table 17 on Page 53, combinations of
SYS_CLKIN and clock multipliers must not select clock rates in
excess of the processor’s maximum instruction rate.
Table 26. Clock and Reset Timing
V
DD_EXT
1.8 V/3.3 V Nominal
Parameter Min Max Unit
Timing Requirements
f
CKIN
SYS_CLKIN Frequency (using a crystal)
1,
2,
3
20 50 MHz
f
CKIN
SYS_CLKIN Frequency (using a crystal oscillator)
1,
2,
3
20 60 MHz
t
CKINL
SYS_CLKIN Low Pulse
1
6.67 ns
t
CKINH
SYS_CLKIN High Pulse
1
6.67 ns
t
WRST
SYS_HWRST Asserted Pulse Width Low
4
11 × t
CKIN
ns
1
Applies to PLL bypass mode and PLL non bypass mode.
2
The t
CKIN
period (see Figure 10) equals 1/f
CKIN
.
3
If the CGU_CTL.DF bit is set, the minimum f
CKIN
specification is 40 MHz.
4
Applies after power-up sequence is complete. See Table 27 and Figure 11 for power-up reset timing.
Figure 10. Clock and Reset Timing
SYS_CLKIN
t
WRST
t
CKIN
t
CKINL
t
CKINH
SYS_HWRST