Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 58 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
PROCESSOR — ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in Table 23 may cause perma-
nent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other condi-
tions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
ESD SENSITIVITY
PROCESSOR — PACKAGE INFORMATION
The information presented in Figure 9 and Table 25 provides
details about package branding. For a complete listing of prod-
uct availability, see Automotive Products on Page 109.
Table 23. Absolute Maximum Ratings
Parameter Rating
Internal Supply Voltage (V
DD_INT
) –0.33 V to 1.32 V
External (I/O) Supply Voltage (V
DD_EXT
) –0.33 V to 3.63 V
Thermal Diode Supply Voltage
(V
DD_TD
)
–0.33 V to 3.63 V
DDR2 Controller Supply Voltage
(V
DD_DMC
)
–0.33 V to 1.90 V
USB PHY Supply Voltage (V
DD_USB
) –0.33 V to 3.63 V
Input Voltage
1, 2, 3
1
Applies to 100% transient duty cycle.
2
Applies only when V
DD_EXT
is within specifications. When V
DD_EXT
is outside
specifications, the range is V
DD_EXT
± 0.2 V.
3
For other duty cycles see Table 24.
–0.33 V to 3.63 V
TWI Input Voltage
2, 4
4
Applies to balls TWI_SCL and TWI_SDA.
–0.33 V to 5.50 V
USB0_Dx Input Voltage
5
5
If the USB is not used, connect USB0_Dx and USB0_VBUS according to Table 15
on Page 37.
–0.33 V to 5.25 V
USB0_VBUS Input Voltage
5
–0.33 V to 6.00 V
DDR2 Input Voltage
6
6
Applies only when V
DD_DMC
is within specifications. When V
DD_DMC
is outside
specifications, the range is V
DD_DMC
± 0.2 V.
–0.33 V to 1.90 V
Output Voltage Swing –0.33 V to V
DD_EXT
+ 0.5 V
I
OH
/I
OL
Current per Signal
1
12.5 mA (max)
Storage Temperature Range –65°C to +150°C
Junction Temperature Under Bias +125°C
Table 24. Maximum Duty Cycle for Input Transient Volt-
age
1,
2
1
Applies to all signal balls with the exception of SYS_CLKIN, SYS_XTAL,
SYS_EXT_WAKE, USB0_DP, USB0_DM, USB0_VBUS, TWI signals, and
DMC0 signals.
2
Applies only when V
DD_EXT
is within specifications. When V
DD_EXT
is outside speci-
fications, the range is V
DD_EXT
±0.2 V.
Maximum Duty Cycle (%)
2
V
IN
Min (V)
3
3
The individual values cannot be combined for analysis of a single instance of
overshoot or undershoot. The worst case observed value must fall within one of
the specified voltages, and the total duration of the overshoot or undershoot
(exceeding the 100% case) must be less than or equal to the corresponding duty
cycle.
V
IN
Max (V)
3
100 –0.33 3.63
50 –0.50 3.80
40 –0.56 3.86
25 –0.67 3.97
20 –0.73 4.03
15 –0.80 4.10
10 –0.90 4.20
Figure 9. Product Information on Package
Table 25. Package Brand Information
Brand Key Field Description
ADSP-BF609 Product Model
t Temperature Range
pp Package Type
Z RoHS Compliant Designation
ccc See Ordering Guide
vvvvvv.x Assembly Lot Code
n.n Silicon Revision
yyww Date Code
ESD
(electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid
performance
degradation or loss of functionality.
tppZccc
ADSP-BF609
a
#yyww country_of_origin
B
vvvvvv.x n.n