Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 56 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Total Internal Power Dissipation
Total power dissipation has two components:
1. Static, including leakage current (deep sleep)
2. Dynamic, due to transistor switching characteristics for
each clock domain
Many operating conditions can also affect power dissipation,
including temperature, voltage, operating frequency, and pro-
cessor activity. The following equation describes the internal
current consumption.
I
DDINT_TOT
= I
DDINT_CCLK_DYN
+ I
DDINT_SYSCLK_DYN
+
I
DDINT_SCLK0_DYN
+ I
DDINT_SCLK1_DYN
+ I
DDINT_DCLK_DYN
+
I
DDINT_USBCLK_DYN
+ I
DDINT_DMA_DR_DYN
+
I
DDINT_DEEPSLEEP
+ I
DDINT_PVP_DYN
I
DDINT_DEEPSLEEP
is the only item present that is part of the static
power dissipation component. I
DDINT_DEEPSLEEP
is specified as a
function of voltage (V
DD_INT
) and temperature (see Table 21).
There are eight different items that contribute to the dynamic
power dissipation. These components fall into three broad cate-
gories: application-dependent currents, clock currents and data
transmission currents.
Application-Dependent Current
The application-dependent currents include the dynamic cur-
rent in the core clock domain and the dynamic current of the
PVP.
Core clock (CCLK) use is subject to an activity scaling factor
(ASF) that represents application code running on the processor
cores and L1/L2 memories (Table 20). The ASF is combined
with the CCLK frequency and V
DD_INT
dependent data in
Table 19 to calculate this portion.
I
DDINT_CCLK_DYN
(mA) = Table 19 × (ASFC0 + ASFC1)
The dynamic current of the PVP is determined by selecting the
appropriate use case from Table 22.
I
DDINT_PVP_DYN
(mA) = Table 22
Clock Current
The dynamic clock currents provide the total power dissipated
by all transistors switching in the clock paths. The power dissi-
pated by each clock domain is dependent on voltage (V
DD_INT
),
operating frequency and a unique scaling factor.
I
DDINT_SYSCLK_DYN
(mA) = 0.187 × f
SYSCLK
(MHz) × V
DD_INT
(V)
I
DDINT_SCLK0_DYN
(mA) = 0.217 × f
SCLK0
(MHz) × V
DD_INT
(V)
I
DDINT_SCLK1_DYN
(mA) = 0.042 × f
SCLK1
(MHz) × V
DD_INT
(V)
I
DDINT_DCLK_DYN
(mA) = 0.024 × f
DCLK
(MHz) × V
DD_INT
(V)
The dynamic component of the USB clock is a unique case. The
USB clock contributes a near constant current value when used.
I
DDINT_USBCLK_DYN
(mA) = 5 mA (if USB enabled)
Data Transmission Current
The data transmission current represents the power dissipated
when transmitting data. This current is expressed in terms of
data rate. The calculation is performed by adding the data rate
(MB/s) of each DMA and core driven access to peripherals and
L2/external memory. This number is then multiplied by a coeffi-
cient and V
DD_INT
. The following equation provides an estimate
of all data transmission current.
I
DDINT_DMA_DR_DYN
(mA) = 0.0578 × data rate (MB/s) × V
DD_INT
(V)
For details on using this equation see the related Engineer Zone
material.
Table 19. CCLK Dynamic Current per core (mA, with ASF = 1)
f
CCLK
(MHz)
Voltage (V
DD_INT
)
1.175 1.200 1.225 1.250 1.275 1.300 1.320
500 96.3 98.8 101.5 103.9 106.7 109.3 110.8
450 87.2 89.5 91.9 94.1 96.7 98.9 100.6
400 78.0 80.1 82.2 84.3 86.5 88.6 90.1
350 68.7 70.7 72.5 74.4 76.3 78.3 79.4
300 59.7 61.2 63.0 64.6 66.3 68.0 69.1
250 50.3 51.8 53.2 54.7 56.3 57.6 58.5
200 41.3 42.4 43.6 44.8 46.0 47.2 48.2
150 32.0 32.9 34.0 34.8 35.9 37.0 37.4
100 22.7 23.5 24.2 25.0 25.7 26.5 26.9