Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 55 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
I
DD_IDLE
23
V
DD_INT
Current in Idle f
CCLK
= 500 MHz
ASFC0 = 0.14 (Idle)
ASFC1 = 0 (Disabled)
f
SYSCLK
= 250 MHz, f
SCLK0/1
= 125 MHz
f
DCLK
= 0 MHz (DDR Disabled)
f
USBCLK
= 0 MHz (USB Disabled)
No PVP or DMA activity
T
J
= 25°C
137 mA
I
DD_TYP
23
V
DD_INT
Current f
CCLK
= 500 MHz
ASFC0 = 1.0 (Full-on Typical)
ASFC1 = 0.86 (App)
f
SYSCLK
= 250 MHz, f
SCLK0/1
= 125 MHz
f
DCLK
= 250 MHz
f
USBCLK
= 0 MHz (USB Disabled)
DMA Data Rate = 124 MB/s
Medium PVP Activity
T
J
= 25°C
357 mA
I
DD_HIBERNATE
22,
24
Hibernate State Current V
DD_INT
= 0 V,
V
DD_EXT
= V
DD_TD
= V
DD_USB
= 3.3 V,
V
DD_DMC
= 1.8 V, V
REF_DMC
= 0.9 V,
T
J
= 25°C, f
CLKIN
= 0 MHz
40 A
I
DD_HIBERNATE
22,
24
Hibernate State Current
Without USB
V
DD_INT
= 0 V,
V
DD_EXT
= V
DD_TD
= V
DD_USB
= 3.3 V,
V
DD_DMC
= 1.8 V, V
REF_DMC
= 0.9 V,
T
J
= 25°C,
f
CLKIN
= 0 MHz, USB protection
disabled (USB0_PHY_CTL.DIS=1)
10 A
I
DD_INT
23
V
DD_INT
Current f
CCLK
> 0 MHz
f
SCLK0/1
≥ 0 MHz
See I
DDINT_TOT
equation
on Page 56
mA
1
Applies to all output and bidirectional signals except DMC0 signals, TWI signals and USB0 signals.
2
Applies to all DMC0 output and bidirectional signals in DDR2 full drive strength mode.
3
Applies to all DMC0 output and bidirectional signals in DDR2 half drive strength mode.
4
Applies to all DMC0 output and bidirectional signals in LPDDR full drive strength mode.
5
Applies to all DMC0 output and bidirectional signals in LPDDR three-quarter drive strength mode.
6
Applies to all DMC0 output and bidirectional signals in LPDDR half drive strength mode.
7
Applies to all DMC0 output and bidirectional signals in LPDDR one-quarter drive strength mode.
8
Applies to all output and bidirectional signals except DMC0 signals and USB0 signals.
9
Applies to signals SMC0_ARDY, SMC0_BR, SYS_BMODE0–2, SYS_CLKIN, SYS_HWRST, SYS_PWRGD, JTG_TDI, and JTG_TMS.
10
Applies to signals JTG_TCK and JTG_TRST.
11
Applies to signals SMC0_ARDY, SMC0_BR, SYS_BMODE0–2, SYS_CLKIN, SYS_HWRST, SYS_PWRGD, JTG_TCK, and JTG_TRST.
12
Applies to signals JTG_TDI, JTG_TMS.
13
Applies to signal USB0_CLKIN.
14
Applies to signals PA0–15, PB0–15, PC0–15, PD0–15, PE0–15, PF0–15, PG0–15, SMC0_AMS0, SMC0_ARE, SMC0_AWE, SMC0_A0E, SMC0_A01–02, SMC0_D00–15, SYS_
FAULT, SYS_FAULT
, JTG_EMU, JTG_TDO, USB0_DM, USB0_DP, USB0_ID, USB0_VBC, USB0_VBUS.
15
Applies to DMC0_A[00:13], DMC0_BA[0:2], DMC0_CAS, DMC0_CS0, DMC0_DQ[00:15], DMC0_LQDS, DMC0_LDQS, DMC0_UDQS, DMC0_UDQS, DMC0_LDM,
DMC0_UDM, DMC0_ODT, DMC0_RAS
, and DMC0_WE.
16
Applies to signals PA0–15, PB0–15, PC0–15, PD0–15, PE0–15, PF0–15, PG0–15, SMC0_A0E, SMC0_A01–02, SMC0_D00–15, SYS_FAULT, SYS_FAULT, JTG_EMU, JTG_
TDO, USB0_DM, USB0_DP, USB0_ID, USB0_VBC, USB0_VBUS, DMC0_A00–13, DMC0_BA0–2, DMC0_CAS
, DMC0_CS0, DMC0_DQ00–15, DMC0_LQDS, DMC0_
LDQS, DMC0_UDQS, DMC0_UDQS, DMC0_LDM, DMC0_UDM, DMC0_ODT, DMC0_RAS, DMC0_WE, and TWI signals.
17
Applies to signals SMC0_AMS0, SMC0_ARE, SMC0_AWE, and when RSI pull-up resistors are enabled, PE10–13, 15 and PG00, 02, 03, 05.
18
Applies to all TWI signals.
19
Applies to all signals, except DMC0 and TWI signals.
20
Guaranteed, but not tested.
21
Applies to all DMC0 signals
22
See the ADSP-BF60x Blackfin Processor Hardware Reference Manual for definition of deep sleep and hibernate operating modes.
23
Additional information can be found at Total Internal Power Dissipation on Page 56.
24
Applies to V
DD_EXT
, V
DD_DMC
, V
DD_USB
and V
DD_TD
supply signals only. Clock inputs are tied high or low.
Parameter Test Conditions Min Typical Max Unit