Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 53 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Clock Related Operating Conditions
Table 17 describes the core clock timing requirements. The data
presented in the tables applies to all speed grades (found in
Automotive Products on Page 109) except where expressly
noted. Figure 8 provides a graphical representation of the vari-
ous clocks and their available divider values.
Table 17. Clock Operating Conditions
Parameter Min Max Unit
f
CCLK
Core Clock Frequency (CCLK ≥ SYSCLK) 500 MHz
f
SYSCLK
SYSCLK Frequency 250 MHz
f
SCLK0
1
SCLK0 Frequency (SYSCLK ≥ SCLK0) 30 125 MHz
f
SCLK1
SCLK1 Frequency (SYSCLK ≥ SCLK1) 125 MHz
f
DCLK
DDR2/LPDDR Clock Frequency (SYSCLK ≥ DCLK) 250 MHz
f
OCLK
Output Clock Frequency 125 MHz
f
PVPCLK
PVP Clock Frequency 83.3 MHz
1
The minimum frequency for SCLK0 applies only when the USB is used.
Table 18. Phase-Locked Loop Operating Conditions
Parameter Min Max Unit
f
PLLCLK
PLL Clock Frequency 250 1000 MHz
Figure 8. Clock Relationships and Divider Values
SYS_CLKIN
PLL
DCLK
SYSCLK
CCLK
SCLK1
(SPORTS, SPI, ACM)
SCLK0
(PVP, ALL OTHER
PERIPHERALS)
CSEL
(1
-
32)
SYSSEL
(1
-
32)
S0SEL
(1
-
4)
S1SEL
(1
-
4)
DSEL
(1
-
32)
OCLK
OSEL
(1
-
128)
PLLCLK