Datasheet

Rev. 0 | Page 52 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
SPECIFICATIONS
For information about product specifications please contact
your ADI representative.
OPERATING CONDITIONS
Parameter Conditions Min Nominal Max Unit
V
DD_INT
Internal Supply Voltage CCLK ≤ 500 MHz 1.19 1.25 1.32 V
V
DD_EXT
1
1
Must remain powered (even if the associated function is not used).
External Supply Voltage 1.7 1.8 1.9 V
V
DD_EXT
1
External Supply Voltage 3.13 3.3 3.47 V
V
DD_DMC
DDR2/LPDDR Supply Voltage 1.7 1.8 1.9 V
V
DD_USB
2
2
If not used, connect to 1.8 V or 3.3 V.
USB Supply Voltage 3.13 3.3 3.47 V
V
DD_TD
Thermal Diode Supply Voltage 3.13 3.3 3.47 V
V
IH
3
3
Parameter value applies to all input and bidirectional signals except TWI signals, DMC0 signals and USB0 signals.
High Level Input Voltage V
DD_EXT
= 3.47 V 2.1 V
V
IH
3
High Level Input Voltage V
DD_EXT
= 1.9 V 0.7 × V
DD_EXT
V
V
IHTWI
4, 5
4
Parameter applies to TWI signals.
5
TWI signals are pulled up to V
BUSTWI
. See Table 16.
High Level Input Voltage V
DD_EXT
= Maximum 0.7 × V
VBUSTWI
V
VBUSTWI
V
V
IH_DDR2
6, 7
6
Parameter applies to DMC0 signals in DDR2 mode.
7
V
DDR_REF
is the voltage applied to pin V
REF_DMC
, nominally V
DD_DMC
/2.
V
DD_DMC
= 1.9 V V
DDR_REF
+ 0.25 V
V
IH_LPDDR
8
8
Parameter applies to DMC0 signals in LPDDR mode.
V
DD_DMC
= 1.9 V 0.8 × V
DD_DMC
V
V
ID_DDR2
9
9
Parameter applies to signals DMC0_CK, DMC0_CK, DMC0_LDQS, DMC0_LDQS, DMC0_UDQS, DMC0_UDQS when used in DDR2 differential input mode.
Differential Input Voltage V
IX
= 1.075 V 0.50 V
V
ID_DDR2
9
Differential Input Voltage V
IX
= 0.725 V 0.55 V
V
IL
3
Low Level Input Voltage V
DD_EXT
= 3.13 V 0.8 V
V
IL
3
Low Level Input Voltage V
DD_EXT
= 1.7 V 0.3 × V
DD_EXT
V
V
ILTWI
4, 5
Low Level Input Voltage V
DD_EXT
= Minimum 0.3 × V
VBUSTWI
V
V
IL_DDR2
6, 7
V
DD_DMC
= 1.7 V V
DDR_REF
– 0.25 V
V
IL_LPDDR
8
V
DD_DMC
= 1.7 V 0.2 × V
DD_DMC
V
T
J
Junction Temperature T
AMBIENT
= –40°C to +85°C –40 +105 °C
T
J
Junction Temperature T
AMBIENT
= –40°C to +105°C –40 +125 °C
Table 16. TWI_VSEL Selections and V
DD_EXT
/V
BUSTWI
V
DD_EXT
Nominal V
BUSTWI
Min V
BUSTWI
Nom V
BUSTWI
Max Unit
TWI000
1
1
Designs must comply with the V
DD_EXT
and V
BUSTWI
voltages specified for the default TWI_DT setting for correct JTAG boundary scan operation during reset.
3.300 3.135 3.300 3.465 V
TWI001 1.800 1.700 1.800 1.900 V
TWI011 1.800 3.135 3.300 3.465 V
TWI100 3.300 4.750 5.000 5.250 V