Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 51 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
USB0_DP I/O F none none none none none VDD_USB Desc: USB0 Data +.
Notes: Pull low if not using USB. For
complete documentation of hibernate
behavior when USB is used, see the USB
chapter in the processor hardware
reference.
USB0_ID I/O na none none none pu none VDD_USB Desc: USB0 OTG ID.
Notes: If USB is not used, connect to
ground. When USB is being used, the
internal pull-up resistor that is present
during hibernate is programmable. See
the USB chapter in the processor
hardware reference. Active during reset.
USB0_VBC I/O E none none none none none VDD_USB Desc: USB0 VBUS Control.
Notes: If USB is not used, pull low.
USB0_VBUS I/O G none none none none none VDD_USB Desc: USB0 Bus Voltage.
Notes: If USB is not used, connect to
ground.
VDD_DMC s na none none none none none na Desc: VDD for DMC.
Notes: If the DMC is not used, connect to
VDD_INT.
VDD_EXT s na none none none none none na Desc: External VDD.
Notes: Must be powered.
VDD_INT s na none none none none none na Desc: Internal VDD.
Notes: Must be powered.
VDD_TD s na none none none none none na Desc: VDD for Thermal Diode.
Notes: If the thermal diode is not used,
connect to ground.
VDD_USB s na none none none none none na Desc: VDD for USB.
Notes: If USB is not used, connect to VDD_
EXT.
VREF_DMC s na none none none none none na Desc: VREF for DMC.
Notes: If the DMC is not used, connect to
VDD_INT.
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Signal Name Type
Driver
Type
Int
Term
Reset
Term
Reset
Drive
Hiber
Ter m
Hiber
Drive
Power
Domain
Description
and Notes