Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 50 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
SYS_PWRGD I/O na none none none none none VDD_EXT Desc: SYS Power Good Indicator.
Notes: If hibernate is not used or the
internal Power Good Counter is used,
connect to VDD_EXT.
SYS_TDA a na none none none none none VDD_TD Desc: SYS Thermal Diode Anode.
Notes: Active during reset and hibernate.
If the thermal diode is not used, connect
to ground.
SYS_TDK a na none none none none none VDD_TD Desc: SYS Thermal Diode Cathode.
Notes: Active during reset and hibernate.
If the thermal diode is not used, connect
to ground.
SYS_XTAL a na none none none none none VDD_EXT Desc: SYS Crystal Output.
Notes: Leave unconnected if an oscillator
is used to provide SYS_CLKIN. Active
during reset. State during hibernate is
controlled by DPM_HIB_DIS.
TWI0_SCL I/O D none none none none none VDD_EXT Desc: TWI0 Serial Clock.
Notes: Open drain, requires external pull-
up resistor. Consult Version 2.1 of the I2C
specification for the proper resistor value.
If TWI is not used, connect to ground.
TWI0_SDA I/O D none none none none none VDD_EXT Desc: TWI0 Serial Data.
Notes: Open drain, requires external pull-
up resistor. Consult Version 2.1 of the I2C
specification for the proper resistor value.
If TWI is not used, connect to ground.
TWI1_SCL I/O D none none none none none VDD_EXT Desc: TWI1 Serial Clock.
Notes: Open drain, requires external pull-
up resistor. Consult Version 2.1 of the I2C
specification for the proper resistor value.
If TWI is not used, connect to ground.
TWI1_SDA I/O D none none none none none VDD_EXT Desc: TWI1 Serial Data.
Notes: Open drain, requires external pull-
up resistor. See the I2C-Bus Specification,
Version 2.1, January 2000 for the proper
resistor value. If TWI is not used, connect
to ground.
USB0_CLKIN a na none none none none none VDD_USB Desc: USB0 Clock/Crystal Input.
Notes: If USB is not used, connect to
ground. Active during reset.
USB0_DM I/O F none none none none none VDD_USB Desc: USB0 Data –.
Notes: Pull low if not using USB. For
complete documentation of hibernate
behavior when USB is used, see the USB
chapter in the processor hardware
reference.
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Signal Name Type
Driver
Type
Int
Term
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
Description
and Notes