Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 49 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
SMC0_D06 I/O A wk wk none wk none VDD_EXT Desc: SMC0 Data 6.
Notes: No notes.
SMC0_D07 I/O A wk wk none wk none VDD_EXT Desc: SMC0 Data 7.
Notes: No notes.
SMC0_D08 I/O A wk wk none wk none VDD_EXT Desc: SMC0 Data 8.
Notes: No notes.
SMC0_D09 I/O A wk wk none wk none VDD_EXT Desc: SMC0 Data 9.
Notes: No notes.
SMC0_D10 I/O A wk wk none wk none VDD_EXT Desc: SMC0 Data 10.
Notes: No notes.
SMC0_D11 I/O A wk wk none wk none VDD_EXT Desc: SMC0 Data 11.
Notes: No notes.
SMC0_D12 I/O A wk wk none wk none VDD_EXT Desc: SMC0 Data 12.
Notes: No notes.
SMC0_D13 I/O A wk wk none wk none VDD_EXT Desc: SMC0 Data 13.
Notes: No notes.
SMC0_D14 I/O A wk wk none wk none VDD_EXT Desc: SMC0 Data 14.
Notes: No notes.
SMC0_D15 I/O A wk wk none wk none VDD_EXT Desc: SMC0 Data 15.
Notes: No notes.
SYS_BMODE0 I/O na none none none none none VDD_EXT Desc: SYS Boot Mode Control 0.
Notes: No notes.
SYS_BMODE1 I/O na none none none none none VDD_EXT Desc: SYS Boot Mode Control 1.
Notes: No notes.
SYS_BMODE2 I/O na none none none none none VDD_EXT Desc: SYS Boot Mode Control 2.
Notes: No notes.
SYS_CLKIN a na none none none none none VDD_EXT Desc: SYS Clock Input/Crystal Input.
Notes: Active during reset.
SYS_CLKOUT I/O A none none L none none VDD_EXT Desc: SYS Processor Clock Output.
Notes: No notes.
SYS_EXTWAKE I/O A none none H none L VDD_EXT Desc: SYS External Wake Control.
Notes: Drives low during hibernate and
high all other times.
SYS_FAULT I/O A none none none none none VDD_EXT Desc: SYS Fault.
Notes: Open source, requires an external
pull-down resistor.
SYS_FAULT
I/O A none none none none none VDD_EXT Desc: SYS Complementary Fault.
Notes: Open drain, requires an external
pull-up resistor.
SYS_HWRST
I/O na none none none none none VDD_EXT Desc: SYS Processor Hardware Reset
Control.
Notes: Active during reset.
SYS_NMI_
RESOUT
I/O A none none L none none VDD_EXT Desc: SYS Reset Output | SYS Non-
maskable Interrupt.
Notes: Requires an external pull-up
resistor.
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Signal Name Type
Driver
Type
Int
Term
Reset
Term
Reset
Drive
Hiber
Ter m
Hiber
Drive
Power
Domain
Description
and Notes