Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 48 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
PG_12 I/O A wk wk none wk none VDD_EXT Desc: PG Position 12 | SPORT2 Channel B
Data 0 | TIMER0 Timer 7 | CNT0 Count
Down and Gate.
Notes: No notes.
PG_13 I/OA wkwknonewknoneVDD_EXTDesc: PG Position 13 | UART1 Clear to
Send | TIMER0 Clock.
Notes: No notes.
PG_14 I/OA wkwknonewknoneVDD_EXTDesc: PG Position 14 | UART1 Receive | SYS
Core 1 Idle Indicator | TIMER0 Alternate
Capture Input 1.
Notes: No notes.
PG_15 I/OA wkwknonewknoneVDD_EXTDesc: PG Position 15 | UART1 Transmit |
SYS Core 0 Idle Indicator | SYS Processor
Sleep Indicator | TIMER0 Alternate
Capture Input 4.
Notes: No notes.
SMC0_A01 I/O A wk wk none wk none VDD_EXT Desc: SMC0 Address 1.
Notes: No notes.
SMC0_A02 I/O A wk wk none wk none VDD_EXT Desc: SMC0 Address 2.
Notes: No notes.
SMC0_AMS0
I/O A pu pu none pu none VDD_EXT Desc: SMC0 Memory Select 0.
Notes: No notes.
SMC0_AOE_
NORDV
I/O A wk wk none wk none VDD_EXT Desc: SMC0 NOR Data Valid | SMC0
Output Enable.
Notes: No notes.
SMC0_ARDY_
NORWT
I/O na none none none none none VDD_EXT Desc: SMC0 NOR Wait | SMC0
Asynchronous Ready.
Notes: Requires an external pull-up
resistor.
SMC0_ARE
I/O A pu pu none pu none VDD_EXT Desc: SMC0 Read Enable.
Notes: No notes.
SMC0_AWE
I/O A pu pu none pu none VDD_EXT Desc: SMC0 Write Enable.
Notes: No notes.
SMC0_BR
I/O na none none none none none VDD_EXT Desc: SMC0 Bus Request.
Notes: Requires an external pull-up
resistor.
SMC0_D00 I/O A wk wk none wk none VDD_EXT Desc: SMC0 Data 0.
Notes: No notes.
SMC0_D01 I/O A wk wk none wk none VDD_EXT Desc: SMC0 Data 1.
Notes: No notes.
SMC0_D02 I/O A wk wk none wk none VDD_EXT Desc: SMC0 Data 2.
Notes: No notes.
SMC0_D03 I/O A wk wk none wk none VDD_EXT Desc: SMC0 Data 3.
Notes: No notes.
SMC0_D04 I/O A wk wk none wk none VDD_EXT Desc: SMC0 Data 4.
Notes: No notes.
SMC0_D05 I/O A wk wk none wk none VDD_EXT Desc: SMC0 Data 5.
Notes: No notes.
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Signal Name Type
Driver
Type
Int
Term
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
Description
and Notes