Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 47 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
PG_02 I/OA wkwknonewknoneVDD_EXTDesc: PG Position 2 | PWM1 Channel A
Low Side | RSI0 Data 1 | ETH1 Transmit
Data 1.
Notes: Has an optional internal pull-up
resistor for use with RSI. See the RSI
chapter in the processor hardware
reference for more details.
PG_03 I/OA wkwknonewknoneVDD_EXTDesc: PG Position 3 | PWM1 Channel A
High Side | RSI0 Data 0 | ETH1 Transmit
Data 0.
Notes: Has an optional internal pull-up
resistor for use with RSI. See the RSI
chapter in the processor hardware
reference for more details.
PG_04 I/OA wkwknonewknoneVDD_EXTDesc: PG Position 4 | SPORT2 Channel A
Clock | TIMER0 Timer 1 | CAN0 Receive |
TIMER0 Alternate Capture Input 2.
Notes: May be used to wake the processor
from hibernate or deep sleep mode.
PG_05 I/OA wkwknonewknoneVDD_EXTDesc: PG Position 5 | RSI0 Command |
ETH1 Transmit Enable | PWM1 Sync |
ACM0 External Trigger 1.
Notes: Has an optional internal pull-up
resistor for use with RSI. See the RSI
chapter in the processor hardware
reference for more details.
PG_06 I/O A wk wk none wk none VDD_EXT Desc: PG Position 6 | RSI0 Clock | SPORT2
Channel B Transmit Data Valid | ETH1
Reference Clock | PWM1 Shutdown Input.
Notes: No notes.
PG_07 I/OA wkwknonewknoneVDD_EXTDesc: PG Position 7 | SPORT2 Channel B
Frame Sync | TIMER0 Timer 5 | CNT0 Count
Zero Marker.
Notes: No notes.
PG_08 I/OA wkwknonewknoneVDD_EXTDesc: PG Position 8 | SPORT2 Channel A
Data 1 | TIMER0 Timer 3 | PWM1
Shutdown Input.
Notes: No notes.
PG_09 I/OA wkwknonewknoneVDD_EXTDesc: PG Position 9 | SPORT2 Channel A
Data 0 | TIMER0 Timer 4.
Notes: No notes.
PG_10 I/OA wkwknonewknoneVDD_EXTDesc: PG Position 10 | UART1 Request to
Send | SPORT2 Channel B Clock.
Notes: No notes.
PG_11 I/OA wkwknonewknoneVDD_EXTDesc: PG Position 11 | SPORT2 Channel B
Data 1 | TIMER0 Timer 6 | CNT0 Count Up
and Direction.
Notes: No notes.
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Signal Name Type
Driver
Type
Int
Term
Reset
Term
Reset
Drive
Hiber
Ter m
Hiber
Drive
Power
Domain
Description
and Notes