Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide

Rev. 0 | Page 46 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
PF_03 I/OA wkwknonewknoneVDD_EXTDesc: PF Position 3 | PWM0 Channel B
High Side | EPPI0 Data 3 | LP2 Data 3.
Notes: No notes.
PF_04 I/O A wk wk none wk none VDD_EXT Desc: PF Position 4 | PWM0 Channel C Low
Side | EPPI0 Data 4 | LP2 Data 4.
Notes: No notes.
PF_05 I/OA wkwknonewknoneVDD_EXTDesc: PF Position 5 | PWM0 Channel C
High Side | EPPI0 Data 5 | LP2 Data 5.
Notes: No notes.
PF_06 I/OA wkwknonewknoneVDD_EXTDesc: PF Position 6 | PWM0 Channel D
Low Side | EPPI0 Data 6 | LP2 Data 6.
Notes: No notes.
PF_07 I/OA wkwknonewknoneVDD_EXTDesc: PF Position 7 | PWM0 Channel D
High Side | EPPI0 Data 7 | LP2 Data 7.
Notes: No notes.
PF_08 I/O A wk wk none wk none VDD_EXT Desc: PF Position 8 | SPI1 Slave Select
Output b | EPPI0 Data 8 | LP3 Data 0.
Notes: No notes.
PF_09 I/O A wk wk none wk none VDD_EXT Desc: PF Position 9 | SPI1 Slave Select
Output b | EPPI0 Data 9 | LP3 Data 1.
Notes: No notes.
PF_10 I/OA wkwknonewknoneVDD_EXTDesc: PF Position 10 | ACM0 Address 4 |
EPPI0 Data 10 | LP3 Data 2.
Notes: No notes.
PF_11 I/O A wk wk none wk none VDD_EXT Desc: PF Position 11 | EPPI0 Data 11 | LP3
Data 3 | PWM0 Shutdown Input.
Notes: No notes.
PF_12 I/OA wkwknonewknoneVDD_EXTDesc: PF Position 12 | ACM0 Address 2 |
EPPI0 Data 12 | LP3 Data 4.
Notes: No notes.
PF_13 I/OA wkwknonewknoneVDD_EXTDesc: PF Position 13 | ACM0 Address 3 |
EPPI0 Data 13 | LP3 Data 5.
Notes: No notes.
PF_14 I/OA wkwknonewknoneVDD_EXTDesc: PF Position 14 | EPPI0 Data 14 |
ACM0 Address 0 | LP3 Data 6.
Notes: No notes.
PF_15 I/OA wkwknonewknoneVDD_EXTDesc: PF Position 15 | ACM0 Address 1 |
EPPI0 Data 15 | LP3 Data 7.
Notes: No notes.
PG_00 I/OA wkwknonewknoneVDD_EXTDesc: PG Position 0 | PWM1 Channel B
High Side | RSI0 Data 2 | ETH1 Receive
Data 0.
Notes: Has an optional internal pull-up
resistor for use with RSI. See the RSI
chapter in the processor hardware
reference for more details.
PG_01 I/OA wkwknonewknoneVDD_EXTDesc: PG Position 1 | SPORT2 Channel A
Frame Sync | TIMER0 Timer 2 | CAN0
Transmit.
Notes: No notes.
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Signal Name Type
Driver
Type
Int
Term
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
Description
and Notes