Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 45 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
PE_10 I/OA wkwknonewknoneVDD_EXTDesc: PE Position 10 | PWM1 Channel D
Low Side | RSI0 Data 6 | ETH1
Management Channel Clock.
Notes: Has an optional internal pull-up
resistor for use with RSI. See the RSI
chapter in the processor hardware
reference for more details.
PE_11 I/OA wkwknonewknoneVDD_EXTDesc: PE Position 11 | PWM1 Channel D
High Side | ETH1 Management Channel
Serial Data | RSI0 Data 7.
Notes: Has an optional internal pull-up
resistor for use with RSI. See the RSI
chapter in the processor hardware
reference for more details.
PE_12 I/OA wkwknonewknoneVDD_EXTDesc: PE Position 12 | PWM1 Channel C
Low Side | RSI0 Data 5 | ETH1 RMII
Management Data Interrupt.
Notes: Has an optional internal pull-up
resistor for use with RSI. See the RSI
chapter in the processor hardware
reference for more details. May be used to
wake the processor from hibernate or
deep sleep mode.
PE_13 I/OA wkwknonewknoneVDD_EXTDesc: PE Position 13 | PWM1 Channel C
High Side | RSI0 Data 4 | ETH1 Carrier
Sense/RMII Receive Data Valid.
Notes: Has an optional internal pull-up
resistor for use with RSI. See the RSI
chapter in the processor hardware
reference for more details.
PE_14 I/OA wkwknonewknoneVDD_EXTDesc: PE Position 14 | SPORT2 Channel A
Transmit Data Valid | TIMER0 Timer 0 |
ETH1 Receive Error.
Notes: No notes.
PE_15 I/OA wkwknonewknoneVDD_EXTDesc: PE Position 15 | PWM1 Channel B
Low Side | RSI0 Data 3 | ETH1 Receive
Data 1.
Notes: Has an optional internal pull-up
resistor for use with RSI. See the RSI
chapter in the processor hardware
reference for more details.
PF_00 I/O A wk wk none wk none VDD_EXT Desc: PF Position 0 | PWM0 Channel A Low
Side | EPPI0 Data 0 | LP2 Data 0.
Notes: No notes.
PF_01 I/OA wkwknonewknoneVDD_EXTDesc: PF Position 1 | PWM0 Channel A
High Side | EPPI0 Data 1 | LP2 Data 1.
Notes: No notes.
PF_02 I/O A wk wk none wk none VDD_EXT Desc: PF Position 2 | PWM0 Channel B Low
Side | EPPI0 Data 2 | LP2 Data 2.
Notes: No notes.
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Signal Name Type
Driver
Type
Int
Term
Reset
Term
Reset
Drive
Hiber
Ter m
Hiber
Drive
Power
Domain
Description
and Notes