Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 43 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
PC_13 I/OA wkwknonewknoneVDD_EXTDesc: PC Position 13 | SPI0 Slave Select
Output b | EPPI1 Data 13 | ETH PTP Clock
Input.
Notes: No notes.
PC_14 I/OA wkwknonewknoneVDD_EXTDesc: PC Position 14 | SPI1 Slave Select
Output b | EPPI1 Data 14.
Notes: No notes.
PC_15 I/OA wkwknonewknoneVDD_EXTDesc: PC Position 15 | SPI0 Slave Select
Output b | EPPI1 Data 15.
Notes: May be used to wake the processor
from hibernate or deep sleep mode.
PD_00 I/OA wkwknonewknoneVDD_EXTDesc: PD Position 0 | SPI0 Data 2 | EPPI1
Data 16 | SPI0 Slave Select Output b.
Notes: No notes.
PD_01 I/OA wkwknonewknoneVDD_EXTDesc: PD Position 1 | SPI0 Data 3 | EPPI1
Data 17 | SPI0 Slave Select Output b.
Notes: No notes.
PD_02 I/OA wkwknonewknoneVDD_EXTDesc: PD Position 2 | SPI0 Master In, Slave
Out.
Notes: No notes.
PD_03 I/OA wkwknonewknoneVDD_EXTDesc: PD Position 3 | SPI0 Master Out,
Slave In.
Notes: No notes.
PD_04 I/OA wkwknonewknoneVDD_EXTDesc: PD Position 4 | SPI0 Clock.
Notes: No notes.
PD_05 I/OA wkwknonewknoneVDD_EXTDesc: PD Position 5 | SPI1 Clock | TIMER0
Alternate Clock 7.
Notes: No notes.
PD_06 I/OA wkwknonewknoneVDD_EXTDesc: PD Position 6 | EPPI1 Frame Sync 2
(VSYNC) | ETH0 RMII Management Data
Interrupt | TIMER0 Alternate Capture
Input 5.
Notes: May be used to wake the processor
from hibernate or deep sleep mode.
PD_07 I/OA wkwknonewknoneVDD_EXTDesc: PD Position 7 | UART0 Transmit |
TIMER0 Alternate Capture Input 3.
Notes: No notes.
PD_08 I/OA wkwknonewknoneVDD_EXTDesc: PD Position 8 | UART0 Receive |
TIMER0 Alternate Capture Input 0.
Notes: No notes.
PD_09 I/O A wk wk none wk none VDD_EXT Desc: PD Position 9 | SPI1 Slave Select
Output b | UART0 Request to Send | SPI0
Slave Select Output b.
Notes: No notes.
PD_10 I/OA wkwknonewknoneVDD_EXTDesc: PD Position 10 | SPI0 Ready | UART0
Clear to Send | SPI1 Slave Select Output b.
Notes: No notes.
PD_11 I/OA wkwknonewknoneVDD_EXTDesc: PD Position 11 | SPI0 Slave Select
Output b | SPI0 Slave Select Input.
Notes: No notes.
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Signal Name Type
Driver
Type
Int
Term
Reset
Term
Reset
Drive
Hiber
Ter m
Hiber
Drive
Power
Domain
Description
and Notes