Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 42 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
PB_13 I/OA wkwknonewknoneVDD_EXTDesc: PB Position 13 | EPPI1 Frame Sync 1
(HSYNC) | ETH0 Transmit Enable | TIMER0
Alternate Capture Input 6.
Notes: No notes.
PB_14 I/OA wkwknonewknoneVDD_EXTDesc: PB Position 14 | EPPI1 Clock | ETH0
Reference Clock.
Notes: No notes.
PB_15 I/OA wkwknonewknoneVDD_EXTDesc: PB Position 15 | EPPI1 Frame Sync 3
(FIELD) | ETH0 PTP Pulse-Per-Second
Output.
Notes: May be used to wake the processor
from hibernate or deep sleep mode.
PC_00 I/OA wkwknonewknoneVDD_EXTDesc: PC Position 0 | EPPI1 Data 0 | ETH0
Receive Data 0.
Notes: No notes.
PC_01 I/OA wkwknonewknoneVDD_EXTDesc: PC Position 1 | EPPI1 Data 1 | ETH0
Receive Data 1.
Notes: No notes.
PC_02 I/OA wkwknonewknoneVDD_EXTDesc: PC Position 2 | EPPI1 Data 2 | ETH0
Transmit Data 0.
Notes: No notes.
PC_03 I/OA wkwknonewknoneVDD_EXTDesc: PC Position 3 | EPPI1 Data 3 | ETH0
Transmit Data 1.
Notes: No notes.
PC_04 I/OA wkwknonewknoneVDD_EXTDesc: PC Position 4 | EPPI1 Data 4 | ETH0
Receive Error.
Notes: No notes.
PC_05 I/OA wkwknonewknoneVDD_EXTDesc: PC Position 5 | EPPI1 Data 5 | ETH0
Carrier Sense/RMII Receive Data Valid.
Notes: No notes.
PC_06 I/OA wkwknonewknoneVDD_EXTDesc: PC Position 6 | EPPI1 Data 6 | ETH0
Management Channel Clock.
Notes: No notes.
PC_07 I/OA wkwknonewknoneVDD_EXTDesc: PC Position 7 | EPPI1 Data 7 | ETH0
Management Channel Serial Data.
Notes: No notes.
PC_08 I/OA wkwknonewknoneVDD_EXTDesc: PC Position 8 | EPPI1 Data 8.
Notes: No notes.
PC_09 I/OA wkwknonewknoneVDD_EXTDesc: PC Position 9 | EPPI1 Data 9 | ETH1
PTP Pulse-Per-Second Output.
Notes: No notes.
PC_10 I/OA wkwknonewknoneVDD_EXTDesc: PC Position 10 | EPPI1 Data 10.
Notes: No notes.
PC_11 I/O A wk wk none wk none VDD_EXT Desc: PC Position 11 | EPPI1 Data 11 | ETH
PTP Auxiliary Trigger Input.
Notes: No notes.
PC_12 I/OA wkwknonewknoneVDD_EXTDesc: PC Position 12 | SPI0 Slave Select
Output b | EPPI1 Data 12.
Notes: No notes.
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Signal Name Type
Driver
Type
Int
Term
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
Description
and Notes