Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 41 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
PB_00 I/O A wk wk none wk none VDD_EXT Desc: PB Position 0 | SMC0 NOR Clock |
EPPI2 Clock | LP0 Clock.
Notes: No notes.
PB_01 I/OA wkwknonewknoneVDD_EXTDesc: PB Position 1 | SMC0 Memory Select
1 | EPPI2 Frame Sync 1 (HSYNC) | LP0
Acknowledge.
Notes: No notes.
PB_02 I/OA wkwknonewknoneVDD_EXTDesc: PB Position 2 | SMC0 Address 13 |
EPPI2 Frame Sync 2 (VSYNC) | LP1
Acknowledge.
Notes: No notes.
PB_03 I/OA wkwknonewknoneVDD_EXTDesc: PB Position 3 | SMC0 Address 16 |
EPPI2 Frame Sync 3 (FIELD) | LP1 Clock.
Notes: No notes.
PB_04 I/OA wkwknonewknoneVDD_EXTDesc: PB Position 4 | SMC0 Memory Select
2 | SMC0 Byte Enable 0 | SPORT0 Channel
A Frame Sync.
Notes: No notes.
PB_05 I/OA wkwknonewknoneVDD_EXTDesc: PB Position 5 | SMC0 Memory Select
3 | SMC0 Byte Enable 1 | SPORT0 Channel
A Clock.
Notes: No notes.
PB_06 I/OA wkwknonewknoneVDD_EXTDesc: PB Position 6 | SMC0 Address 21 |
SPORT0 Channel A Transmit Data Valid |
TIMER0 Alternate Clock 4.
Notes: No notes.
PB_07 I/OA wkwknonewknoneVDD_EXTDesc: PB Position 7 | SMC0 Address 22 |
EPPI2 Data 16 | SPORT0 Channel B Frame
Sync.
Notes: No notes.
PB_08 I/OA wkwknonewknoneVDD_EXTDesc: PB Position 8 | SMC0 Address 23 |
EPPI2 Data 17 | SPORT0 Channel B Clock.
Notes: No notes.
PB_09 I/OA wkwknonewknoneVDD_EXTDesc: PB Position 9 | SMC0 Bus Grant Hang
| SPORT0 Channel A Data 0 | TIMER0
Alternate Clock 2.
Notes: No notes.
PB_10 I/O A wk wk none wk none VDD_EXT Desc: PB Position 10 | SMC0 Address 24 |
SPORT0 Channel B Data 1 | TIMER0
Alternate Clock 0.
Notes: No notes.
PB_11 I/O A wk wk none wk none VDD_EXT Desc: PB Position 11 | SMC0 Address 25 |
SPORT0 Channel B Data 0 | TIMER0
Alternate Clock 3.
Notes: No notes.
PB_12 I/OA wkwknonewknoneVDD_EXTDesc: PB Position 12 | SMC0 Bus Grant |
SPORT0 Channel B Transmit Data Valid |
SPORT0 Channel A Data 1 | TIMER0
Alternate Clock 1.
Notes: No notes.
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Signal Name Type
Driver
Type
Int
Term
Reset
Term
Reset
Drive
Hiber
Ter m
Hiber
Drive
Power
Domain
Description
and Notes