Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 40 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
PA_00 I/O A wk wk none wk none VDD_EXT Desc: PA Position 0 | SMC0 Address 3 |
EPPI2 Data 0 | LP0 Data 0.
Notes: No notes.
PA_01 I/O A wk wk none wk none VDD_EXT Desc: PA Position 1 | SMC0 Address 4 |
EPPI2 Data 1 | LP0 Data 1.
Notes: No notes.
PA_02 I/O A wk wk none wk none VDD_EXT Desc: PA Position 2 | SMC0 Address 5 |
EPPI2 Data 2 | LP0 Data 2.
Notes: No notes.
PA_03 I/O A wk wk none wk none VDD_EXT Desc: PA Position 3 | SMC0 Address 6 |
EPPI2 Data 3 | LP0 Data 3.
Notes: No notes.
PA_04 I/O A wk wk none wk none VDD_EXT Desc: PA Position 4 | SMC0 Address 7 |
EPPI2 Data 4 | LP0 Data 4.
Notes: No notes.
PA_05 I/O A wk wk none wk none VDD_EXT Desc: PA Position 5 | SMC0 Address 8 |
EPPI2 Data 5 | LP0 Data 5.
Notes: No notes.
PA_06 I/O A wk wk none wk none VDD_EXT Desc: PA Position 6 | SMC0 Address 9 |
EPPI2 Data 6 | LP0 Data 6.
Notes: No notes.
PA_07 I/O A wk wk none wk none VDD_EXT Desc: PA Position 7 | SMC0 Address 10 |
EPPI2 Data 7 | LP0 Data 7.
Notes: No notes.
PA_08 I/O A wk wk none wk none VDD_EXT Desc: PA Position 8 | SMC0 Address 11 |
EPPI2 Data 8 | LP1 Data 0.
Notes: No notes.
PA_09 I/O A wk wk none wk none VDD_EXT Desc: PA Position 9 | SMC0 Address 12 |
EPPI2 Data 9 | LP1 Data 1.
Notes: No notes.
PA_10 I/O A wk wk none wk none VDD_EXT Desc: PA Position 10 | SMC0 Address 14 |
EPPI2 Data 10 | LP1 Data 2.
Notes: No notes.
PA_11 I/O A wk wk none wk none VDD_EXT Desc: PA Position 11 | SMC0 Address 15 |
EPPI2 Data 11 | LP1 Data 3.
Notes: No notes.
PA_12 I/O A wk wk none wk none VDD_EXT Desc: PA Position 12 | SMC0 Address 17 |
EPPI2 Data 12 | LP1 Data 4.
Notes: No notes.
PA_13 I/O A wk wk none wk none VDD_EXT Desc: PA Position 13 | SMC0 Address 18 |
EPPI2 Data 13 | LP1 Data 5.
Notes: No notes.
PA_14 I/O A wk wk none wk none VDD_EXT Desc: PA Position 14 | SMC0 Address 19 |
EPPI2 Data 14 | LP1 Data 6.
Notes: No notes.
PA_15 I/O A wk wk none wk none VDD_EXT Desc: PA Position 15 | SMC0 Address 20 |
EPPI2 Data 15 | LP1 Data 7.
Notes: May be used to wake the processor
from hibernate or deep sleep mode.
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Signal Name Type
Driver
Type
Int
Term
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
Description
and Notes