Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide

Rev. 0 | Page 39 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
DMC0_DQ13 I/O B none none none none none VDD_DMC Desc: DMC0 Data 13.
Notes: No notes.
DMC0_DQ14 I/O B none none none none none VDD_DMC Desc: DMC0 Data 14.
Notes: No notes.
DMC0_DQ15 I/O B none none none none none VDD_DMC Desc: DMC0 Data 15.
Notes: No notes.
DMC0_LDM I/O B none none none none none VDD_DMC Desc: DMC0 Data Mask for Lower Byte.
Notes: No notes.
DMC0_LDQS I/O C none none none none none VDD_DMC Desc: DMC0 Data Strobe for Lower Byte.
Notes: For LPDDR, a 100k ohm pull-down
resistor is required.
DMC0_LDQS
I/O C none none none none none VDD_DMC Desc: DMC0 Data Strobe for Lower Byte
(complement).
Notes: For single ended DDR2, connect to
VREF_DMC. For LPDDR, leave
unconnected.
DMC0_ODT I/O B none none none none none VDD_DMC Desc: DMC0 On-die termination.
Notes: For LPDDR, leave unconnected.
DMC0_RAS
I/O B none none none none none VDD_DMC Desc: DMC0 Row Address Strobe.
Notes: No notes.
DMC0_UDM I/O B none none none none none VDD_DMC Desc: DMC0 Data Mask for Upper Byte.
Notes: No notes.
DMC0_UDQS I/O C none none none none none VDD_DMC Desc: DMC0 Data Strobe for Upper Byte.
Notes: For LPDDR, a 100k ohm pull-down
resistor is required.
DMC0_UDQS
I/O C none none none none none VDD_DMC Desc: DMC0 Data Strobe for Upper Byte
(complement).
Notes: For single ended DDR2, connect to
VREF_DMC. For LPDDR, leave
unconnected.
DMC0_WE
I/O B none none none none none VDD_DMC Desc: DMC0 Write Enable.
Notes: No notes.
GND g na none none none none none na Desc: Ground.
Notes: No notes.
JTG_EMU
I/O A none none none none none VDD_EXT Desc: Emulation Output.
Notes: No notes.
JTG_TCK I/O na pd none none none none VDD_EXT Desc: JTG Clock.
Notes: Functional during reset.
JTG_TDI I/O na pu none none none none VDD_EXT Desc: JTG Serial Data Input.
Notes: Functional during reset.
JTG_TDO I/O A none none none none none VDD_EXT Desc: JTG Serial Data Output.
Notes: Functional during reset, three-
state when JTG_TRST
is asserted.
JTG_TMS I/O na pu none none none none VDD_EXT Desc: JTG Mode Select.
Notes: Functional during reset.
JTG_TRST
I/O na pd none none none none VDD_EXT Desc: JTG Reset.
Notes: Functional during reset.
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Signal Name Type
Driver
Type
Int
Term
Reset
Term
Reset
Drive
Hiber
Ter m
Hiber
Drive
Power
Domain
Description
and Notes