Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 38 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
DMC0_A11 I/O B none none none none none VDD_DMC Desc: DMC0 Address 11.
Notes: No notes.
DMC0_A12 I/O B none none none none none VDD_DMC Desc: DMC0 Address 12.
Notes: No notes.
DMC0_A13 I/O B none none none none none VDD_DMC Desc: DMC0 Address 13.
Notes: No notes.
DMC0_BA0 I/O B none none none none none VDD_DMC Desc: DMC0 Bank Address Input 0.
Notes: No notes.
DMC0_BA1 I/O B none none none none none VDD_DMC Desc: DMC0 Bank Address Input 1.
Notes: No notes.
DMC0_BA2 I/O B none none none none none VDD_DMC Desc: DMC0 Bank Address Input 2.
Notes: For LPDDR, leave unconnected.
DMC0_CAS
I/O B none none none none none VDD_DMC Desc: DMC0 Column Address Strobe.
Notes: No notes.
DMC0_CK I/O C none none L none L VDD_DMC Desc: DMC0 Clock.
Notes: No notes.
DMC0_CK
I/O C none none L none L VDD_DMC Desc: DMC0 Clock (complement).
Notes: No notes.
DMC0_CKE I/O B none none L none L VDD_DMC Desc: DMC0 Clock enable.
Notes: No notes.
DMC0_CS0
I/O B none none none none none VDD_DMC Desc: DMC0 Chip Select 0.
Notes: No notes.
DMC0_DQ00 I/O B none none none none none VDD_DMC Desc: DMC0 Data 0.
Notes: No notes.
DMC0_DQ01 I/O B none none none none none VDD_DMC Desc: DMC0 Data 1.
Notes: No notes.
DMC0_DQ02 I/O B none none none none none VDD_DMC Desc: DMC0 Data 2.
Notes: No notes.
DMC0_DQ03 I/O B none none none none none VDD_DMC Desc: DMC0 Data 3.
Notes: No notes.
DMC0_DQ04 I/O B none none none none none VDD_DMC Desc: DMC0 Data 4.
Notes: No notes.
DMC0_DQ05 I/O B none none none none none VDD_DMC Desc: DMC0 Data 5.
Notes: No notes.
DMC0_DQ06 I/O B none none none none none VDD_DMC Desc: DMC0 Data 6.
Notes: No notes.
DMC0_DQ07 I/O B none none none none none VDD_DMC Desc: DMC0 Data 7.
Notes: No notes.
DMC0_DQ08 I/O B none none none none none VDD_DMC Desc: DMC0 Data 8.
Notes: No notes.
DMC0_DQ09 I/O B none none none none none VDD_DMC Desc: DMC0 Data 9.
Notes: No notes.
DMC0_DQ10 I/O B none none none none none VDD_DMC Desc: DMC0 Data 10.
Notes: No notes.
DMC0_DQ11 I/O B none none none none none VDD_DMC Desc: DMC0 Data 11.
Notes: No notes.
DMC0_DQ12 I/O B none none none none none VDD_DMC Desc: DMC0 Data 12.
Notes: No notes.
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Signal Name Type
Driver
Type
Int
Term
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
Description
and Notes