Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 37 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
ADSP-BF60x DESIGNER QUICK REFERENCE
The table provides a quick reference summary of pin related
information for circuit board design. The columns in this table
provide the following information:
• Signal Name: The Signal Name column in the table
includes the Signal Name for every pin.
• Type: The Pin Type column in the table identifies the I/O
type or supply type of the pin. The abbreviations used in
this column are na (None), I/O (Digital input and/or out-
put), a (Analog), s (Supply), and g (Ground).
• Driver Type: The Driver Type column in the table identi-
fies the driver type used by the pin. The driver types are
defined in Output Drive Currents on Page 99.
• Int Term: The Internal Termination column in the table
specifies the termination present when the processor is not
in the reset or hibernate state. The abbreviations used in
this column are wk (Weak Keeper, weakly retains previous
value driven on the pin), pu (Pull-up resistor), or pd (Pull-
down resistor).
• Reset Term: The Reset Termination column in the table
specifies the termination present when the processor is in
the reset state. The abbreviations used in this column are
wk (Weak Keeper, weakly retains previous value driven on
the pin), pu (Pull-up resistor), or pd (Pull-down resistor).
• Reset Drive: The Reset Drive column in the table specifies
the active drive on the signal when the processor is in the
reset state.
• Hiber Term: The Hibernate Termination column in the
table specifies the termination present when the processor
is in the hibernate state. The abbreviations used in this col-
umn are wk (Weak Keeper, weakly retains previous value
driven on the pin), pu (Pull-up resistor), or pd (Pull-down
resistor).
• Hiber Drive: The Hibernate Drive column in the table
specifies the active drive on the signal when the processor is
in the hibernate state.
• Power Domain: The Power Domain column in the table
specifies the power supply domain in which the signal
resides.
• Description and Notes: The Description and Notes column
in the table identifies any special requirements or charac-
teristics for the signal. If no special requirements are listed
the signal may be left unconnected if it is not used. Also, for
multiplexed general-purpose I/O pins, this column identi-
fies the functions available on the pin.
Table 15. ADSP-BF60x Designer Quick Reference
Signal Name Type
Driver
Type
Int
Term
Reset
Term
Reset
Drive
Hiber
Ter m
Hiber
Drive
Power
Domain
Description
and Notes
DMC0_A00 I/O B none none none none none VDD_DMC Desc: DMC0 Address 0.
Notes: No notes.
DMC0_A01 I/O B none none none none none VDD_DMC Desc: DMC0 Address 1.
Notes: No notes.
DMC0_A02 I/O B none none none none none VDD_DMC Desc: DMC0 Address 2.
Notes: No notes.
DMC0_A03 I/O B none none none none none VDD_DMC Desc: DMC0 Address 3.
Notes: No notes.
DMC0_A04 I/O B none none none none none VDD_DMC Desc: DMC0 Address 4.
Notes: No notes.
DMC0_A05 I/O B none none none none none VDD_DMC Desc: DMC0 Address 5.
Notes: No notes.
DMC0_A06 I/O B none none none none none VDD_DMC Desc: DMC0 Address 6.
Notes: No notes.
DMC0_A07 I/O B none none none none none VDD_DMC Desc: DMC0 Address 7.
Notes: No notes.
DMC0_A08 I/O B none none none none none VDD_DMC Desc: DMC0 Address 8.
Notes: No notes.
DMC0_A09 I/O B none none none none none VDD_DMC Desc: DMC0 Address 9.
Notes: No notes.
DMC0_A10 I/O B none none none none none VDD_DMC Desc: DMC0 Address 10.
Notes: No notes.