Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 36 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 14. Signal Multiplexing for Port G
Signal Name Multiplexed Function 0 Multiplexed Function 1 Multiplexed Function 2
Multiplexed Function
Input Tap
PG_00 ETH1_RXD0 PWM1_BH RSI0_D2
PG_01 SPT2_AFS TM0_TMR2 CAN0_TX
PG_02 ETH1_TXD1 PWM1_AL RSI0_D1
PG_03 ETH1_TXD0 PWM1_AH RSI0_D0
PG_04 SPT2_ACLK TM0_TMR1 CAN0_RX TM0_ACI2
PG_05 ETH1_TXEN RSI0_CMD PWM1_SYNC ACM0_T1
PG_06 ETH1_REFCLK RSI0_CLK SPT2_BTDV PWM1_TRIP0
PG_07 SPT2_BFS TM0_TMR5 CNT0_ZM
PG_08 SPT2_AD1 TM0_TMR3 PWM1_TRIP1
PG_09 SPT2_AD0 TM0_TMR4
PG_10 UART1_RTS
SPT2_BCLK
PG_11 SPT2_BD1 TM0_TMR6 CNT0_UD
PG_12 SPT2_BD0 TM0_TMR7 CNT0_DG
PG_13 UART1_CTS
TM0_CLK
PG_14 UART1_RX
SYS_IDLE1 TM0_ACI1
PG_15 UART1_TX
SYS_IDLE0 SYS_SLEEP TM0_ACI4