Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 35 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 12. Signal Multiplexing for Port E
Signal Name Multiplexed Function 0 Multiplexed Function 1 Multiplexed Function 2
Multiplexed Function
Input Tap
PE_00 SPI1_D3 PPI0_D18 SPT1_BD1
PE_01 SPI1_D2 PPI0_D19 SPT1_BD0
PE_02 SPI1_RDY PPI0_D22 SPT1_ACLK
PE_03 PPI0_D16 ACM0_FS/SPT1_BFS
PE_04 PPI0_D17 ACM0_CLK/SPT1_BCLK
PE_05 PPI0_D23 SPT1_AFS
PE_06 SPT1_ATDV PPI0_FS3 LP3_CLK
PE_07 SPT1_BTDV PPI0_FS2 LP3_ACK
PE_08 PWM0_SYNC PPI0_FS1 LP2_ACK ACM0_T0
PE_09 PPI0_CLK LP2_CLK PWM0_TRIP0
PE_10 ETH1_MDC PWM1_DL RSI0_D6
PE_11 ETH1_MDIO PWM1_DH RSI0_D7
PE_12 PWM1_CL RSI0_D5
PE_13 ETH1_CRS PWM1_CH RSI0_D4
PE_14 SPT2_ATDV TM0_TMR0
PE_15 ETH1_RXD1 PWM1_BL RSI0_D3
Table 13. Signal Multiplexing for Port F
Signal Name Multiplexed Function 0 Multiplexed Function 1 Multiplexed Function 2
Multiplexed Function
Input Tap
PF_00 PWM0_AL PPI0_D00 LP2_D0
PF_01 PWM0_AH PPI0_D01 LP2_D1
PF_02 PWM0_BL PPI0_D02 LP2_D2
PF_03 PWM0_BH PPI0_D03 LP2_D3
PF_04 PWM0_CL PPI0_D04 LP2_D4
PF_05 PWM0_CH PPI0_D05 LP2_D5
PF_06 PWM0_DL PPI0_D06 LP2_D6
PF_07 PWM0_DH PPI0_D07 LP2_D7
PF_08 SPI1_SEL5
PPI0_D08 LP3_D0
PF_09 SPI1_SEL6
PPI0_D09 LP3_D1
PF_10 ACM0_A4 PPI0_D10 LP3_D2
PF_11 PPI0_D11 LP3_D3 PWM0_TRIP1
PF_12 ACM0_A2 PPI0_D12 LP3_D4
PF_13 ACM0_A3 PPI0_D13 LP3_D5
PF_14 ACM0_A0 PPI0_D14 LP3_D6
PF_15 ACM0_A1 PPI0_D15 LP3_D7