Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 34 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 10. Signal Multiplexing for Port C
Signal Name Multiplexed Function 0 Multiplexed Function 1 Multiplexed Function 2
Multiplexed Function
Input Tap
PC_00 ETH0_RXD0 PPI1_D00
PC_01 ETH0_RXD1 PPI1_D01
PC_02 ETH0_TXD0 PPI1_D02
PC_03 ETH0_TXD1 PPI1_D03
PC_04 PPI1_D04
PC_05 ETH0_CRS PPI1_D05
PC_06 ETH0_MDC PPI1_D06
PC_07 ETH0_MDIO PPI1_D07
PC_08 PPI1_D08
PC_09 ETH1_PTPPPS PPI1_D09
PC_10 PPI1_D10
PC_11 PPI1_D11 ETH_PTPAUXIN
PC_12 SPI0_SEL7
PPI1_D12
PC_13 SPI0_SEL6
PPI1_D13 ETH_PTPCLKIN
PC_14 SPI1_SEL7
PPI1_D14
PC_15 SPI0_SEL4
PPI1_D15
Table 11. Signal Multiplexing for Port D
Signal Name Multiplexed Function 0 Multiplexed Function 1 Multiplexed Function 2
Multiplexed Function
Input Tap
PD_00 SPI0_D2 PPI1_D16 SPI0_SEL3
PD_01 SPI0_D3 PPI1_D17 SPI0_SEL2
PD_02 SPI0_MISO
PD_03 SPI0_MOSI
PD_04 SPI0_CLK
PD_05 SPI1_CLK TM0_ACLK7
PD_06 PPI1_FS2 TM0_ACI5
PD_07 UART0_TX
TM0_ACI3
PD_08 UART0_RX
TM0_ACI0
PD_09 SPI0_SEL5
UART0_RTS SPI1_SEL4
PD_10 SPI0_RDY UART0_CTS SPI1_SEL3
PD_11 SPI0_SEL1 SPI0_SS
PD_12 SPI1_SEL1 PPI0_D20 SPT1_AD1 SPI1_SS
PD_13 SPI1_MOSI TM0_ACLK5
PD_14 SPI1_MISO TM0_ACLK6
PD_15 SPI1_SEL2
PPI0_D21 SPT1_AD0