Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 33 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
GP I/O MULTIPLEXING FOR 349-BALL CSP_BGA
Table 8 through Table 14 identifies the pin functions that are
multiplexed on the general-purpose I/O pins of the 349-ball
CSP_BGA package.
Table 8. Signal Multiplexing for Port A
Signal Name Multiplexed Function 0 Multiplexed Function 1 Multiplexed Function 2
Multiplexed Function
Input Tap
PA_00 SMC0_A03 PPI2_D00 LP0_D0
PA_01 SMC0_A04 PPI2_D01 LP0_D1
PA_02 SMC0_A05 PPI2_D02 LP0_D2
PA_03 SMC0_A06 PPI2_D03 LP0_D3
PA_04 SMC0_A07 PPI2_D04 LP0_D4
PA_05 SMC0_A08 PPI2_D05 LP0_D5
PA_06 SMC0_A09 PPI2_D06 LP0_D6
PA_07 SMC0_A10 PPI2_D07 LP0_D7
PA_08 SMC0_A11 PPI2_D08 LP1_D0
PA_09 SMC0_A12 PPI2_D09 LP1_D1
PA_10 SMC0_A14 PPI2_D10 LP1_D2
PA_11 SMC0_A15 PPI2_D11 LP1_D3
PA_12 SMC0_A17 PPI2_D12 LP1_D4
PA_13 SMC0_A18 PPI2_D13 LP1_D5
PA_14 SMC0_A19 PPI2_D14 LP1_D6
PA_15 SMC0_A20 PPI2_D15 LP1_D7
Table 9. Signal Multiplexing for Port B
Signal Name Multiplexed Function 0 Multiplexed Function 1 Multiplexed Function 2
Multiplexed Function
Input Tap
PB_00 SMC0_NORCLK PPI2_CLK LP0_CLK
PB_01 SMC0_AMS1
PPI2_FS1 LP0_ACK
PB_02 SMC0_A13 PPI2_FS2 LP1_ACK
PB_03 SMC0_A16 PPI2_FS3 LP1_CLK
PB_04 SMC0_AMS2
SMC0_ABE0 SPT0_AFS
PB_05 SMC0_AMS3
SMC0_ABE1 SPT0_ACLK
PB_06 SMC0_A21 SPT0_ATDV TM0_ACLK4
PB_07 SMC0_A22 PPI2_D16 SPT0_BFS
PB_08 SMC0_A23 PPI2_D17 SPT0_BCLK
PB_09 SMC0_BGH
SPT0_AD0 TM0_ACLK2
PB_10 SMC0_A24 SPT0_BD1 TM0_ACLK0
PB_11 SMC0_A25 SPT0_BD0 TM0_ACLK3
PB_12 SMC0_BG
SPT0_BTDV SPT0_AD1 TM0_ACLK1
PB_13 ETH0_TXEN PPI1_FS1 TM0_ACI6
PB_14 ETH0_REFCLK PPI1_CLK
PB_15 ETH0_PTPPPS PPI1_FS3