Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 32 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
UART0_RX UART0 Receive D PD_08
UART0_TX
UART0 Transmit D PD_07
UART1_CTS
UART1 Clear to Send G PG_13
UART1_RTS
UART1 Request to Send G PG_10
UART1_RX
UART1 Receive G PG_14
UART1_TX
UART1 Transmit G PG_15
USB0_CLKIN USB0 Clock/Crystal Input Not Muxed USB0_CLKIN
USB0_DM USB0 Data – Not Muxed USB0_DM
USB0_DP USB0 Data + Not Muxed USB0_DP
USB0_ID USB0 OTG ID Not Muxed USB0_ID
USB0_VBC USB0 VBUS Control Not Muxed USB0_VBC
USB0_VBUS USB0 Bus Voltage Not Muxed USB0_VBUS
VDD_DMC VDD for DMC Not Muxed VDD_DMC
VDD_EXT External VDD Not Muxed VDD_EXT
VDD_INT Internal VDD Not Muxed VDD_INT
VDD_TD VDD for Thermal Diode Not Muxed VDD_TD
VDD_USB VDD for USB Not Muxed VDD_USB
VREF_DMC VREF for DMC Not Muxed VREF_DMC
Table 7. ADSP-BF60x 349-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name Description Port Pin Name