Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 30 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
SPI1_CLK SPI1 Clock D PD_05
SPI1_D2 SPI1 Data 2 E PE_01
SPI1_D3 SPI1 Data 3 E PE_00
SPI1_MISO SPI1 Master In, Slave Out D PD_14
SPI1_MOSI SPI1 Master Out, Slave In D PD_13
SPI1_RDY SPI1 Ready E PE_02
SPI1_SEL1
SPI1 Slave Select Output 1 D PD_12
SPI1_SEL2
SPI1 Slave Select Output 2 D PD_15
SPI1_SEL3
SPI1 Slave Select Output 3 D PD_10
SPI1_SEL4
SPI1 Slave Select Output 4 D PD_09
SPI1_SEL5
SPI1 Slave Select Output 5 F PF_08
SPI1_SEL6
SPI1 Slave Select Output 6 F PF_09
SPI1_SEL7
SPI1 Slave Select Output 7 C PC_14
SPI1_SS
SPI1 Slave Select Input D PD_12
SPT0_ACLK SPORT0 Channel A Clock B PB_05
SPT0_AD0 SPORT0 Channel A Data 0 B PB_09
SPT0_AD1 SPORT0 Channel A Data 1 B PB_12
SPT0_AFS SPORT0 Channel A Frame Sync B PB_04
SPT0_ATDV SPORT0 Channel A Transmit Data Valid B PB_06
SPT0_BCLK SPORT0 Channel B Clock B PB_08
SPT0_BD0 SPORT0 Channel B Data 0 B PB_11
SPT0_BD1 SPORT0 Channel B Data 1 B PB_10
SPT0_BFS SPORT0 Channel B Frame Sync B PB_07
SPT0_BTDV SPORT0 Channel B Transmit Data Valid B PB_12
SPT1_ACLK SPORT1 Channel A Clock E PE_02
SPT1_AD0 SPORT1 Channel A Data 0 D PD_15
SPT1_AD1 SPORT1 Channel A Data 1 D PD_12
SPT1_AFS SPORT1 Channel A Frame Sync E PE_05
SPT1_ATDV SPORT1 Channel A Transmit Data Valid E PE_06
SPT1_BCLK SPORT1 Channel B Clock E PE_04
SPT1_BD0 SPORT1 Channel B Data 0 E PE_01
SPT1_BD1 SPORT1 Channel B Data 1 E PE_00
SPT1_BFS SPORT1 Channel B Frame Sync E PE_03
SPT1_BTDV SPORT1 Channel B Transmit Data Valid E PE_07
SPT2_ACLK SPORT2 Channel A Clock G PG_04
SPT2_AD0 SPORT2 Channel A Data 0 G PG_09
SPT2_AD1 SPORT2 Channel A Data 1 G PG_08
SPT2_AFS SPORT2 Channel A Frame Sync G PG_01
SPT2_ATDV SPORT2 Channel A Transmit Data Valid E PE_14
SPT2_BCLK SPORT2 Channel B Clock G PG_10
SPT2_BD0 SPORT2 Channel B Data 0 G PG_12
SPT2_BD1 SPORT2 Channel B Data 1 G PG_11
SPT2_BFS SPORT2 Channel B Frame Sync G PG_07
SPT2_BTDV SPORT2 Channel B Transmit Data Valid G PG_06
SYS_BMODE0 Boot Mode Control 0 Not Muxed SYS_BMODE0
SYS_BMODE1 Boot Mode Control 1 Not Muxed SYS_BMODE1
Table 7. ADSP-BF60x 349-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name Description Port Pin Name