Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 3 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
GENERAL DESCRIPTION
The ADSP-BF60x processors are members of the Blackfin
family of products, incorporating the Analog Devices/Intel
Micro Signal Architecture (MSA). Blackfin processors combine
a dual-MAC state-of-the-art signal processing engine, the
advantages of a clean, orthogonal RISC-like microprocessor
instruction set, and single-instruction, multiple-data (SIMD)
multimedia capabilities into a single instruction-set
architecture.
The processors offer performance up to 500 MHz, as well as low
static power consumption. Produced with a low-power and low-
voltage design methodology, they provide world-class power
management and performance.
By integrating a rich set of industry-leading system peripherals
and memory (shown in Table 1), Blackfin processors are the
platform of choice for next-generation applications that require
RISC-like programmability, multimedia support, and leading-
edge signal processing in one integrated package. These applica-
tions span a wide array of markets, from automotive systems to
embedded industrial, instrumentation and power/motor con-
trol applications.
BLACKFIN PROCESSOR CORE
As shown in Figure 1, the processor integrates two Blackfin pro-
cessor cores. Each core, shown in Figure 2, contains two 16-bit
multipliers, two 40-bit accumulators, two 40-bit ALUs, four
video ALUs, and a 40-bit shifter. The computation units process
8-, 16-, or 32-bit data from the register file.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation
are supported.
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and pop-
ulation count, modulo 2
32
multiply, divide primitives, saturation
and rounding, and sign/exponent detection. The set of video
instructions include byte alignment and packing operations,
16-bit and 8-bit adds with clipping, 8-bit average operations,
and 8-bit subtract/absolute value/accumulate (SAA) operations.
Also provided are the compare/select and vector search
instructions.
For certain instructions, two 16-bit ALU operations can be per-
formed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). If the second ALU is used,
quad 16-bit operations are possible.
Table 1. Processor Comparison
Processor Feature
ADSP-BF606
ADSP-BF607
ADSP-BF608
ADSP-BF609
Up/Down/Rotary Counters 1
Timer/Counters with PWM 8
3-Phase PWM Units (4-pair) 2
SPORTs 3
SPIs 2
USB OTG 1
Parallel Peripheral Interface 3
Removable Storage Interface 1
CAN 1
TWI 2
UART 2
ADC Control Module (ACM) 1
Link Ports 4
Ethernet MAC (IEEE 1588) 2
Pixel Compositor (PIXC) No 1 1
Pipelined Vision Processor
(PVP) Video Resolution
1
No VGA HD
Maximum PVP Line Buffer Size N/A 640 1280
GPIOs 112
Memory (bytes, per core)
L1 Instruction SRAM 64K
L1 Instruction SRAM/Cache 16K
L1 Data SRAM 32K
L1 Data SRAM/Cache 32K
L1 Scratchpad 4K
L2 Data SRAM 128K 256K
L2 Boot ROM 32K
Maximum Speed Grade (MHz)
2
400 500
Maximum SYSCLK (MHz)
250
Package Options 349-Ball CSP_BGA
1
VGA is 640 × 480 pixels per frame. HD is 1280 × 960 pixels per frame.
2
Maximum speed grade is not available with every possible SYSCLK selection.
Table 1. Processor Comparison (Continued)
Processor Feature
ADSP-BF606
ADSP-BF607
ADSP-BF608
ADSP-BF609