Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 29 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
SMC0_ABE0 SMC0 Byte Enable 0 B PB_04
SMC0_ABE1
SMC0 Byte Enable 1 B PB_05
SMC0_AMS0
SMC0 Memory Select 0 Not Muxed SMC0_AMS0
SMC0_AMS1 SMC0 Memory Select 1 B PB_01
SMC0_AMS2
SMC0 Memory Select 2 B PB_04
SMC0_AMS3
SMC0 Memory Select 3 B PB_05
SMC0_AOE
SMC0 Output Enable Not Muxed SMC0_AOE_NORDV
SMC0_ARDY SMC0 Asynchronous Ready Not Muxed SMC0_ARDY_NORWT
SMC0_ARE
SMC0 Read Enable Not Muxed SMC0_ARE
SMC0_AWE SMC0 Write Enable Not Muxed SMC0_AWE
SMC0_BGH SMC0 Bus Grant Hang B PB_09
SMC0_BG
SMC0 Bus Grant B PB_12
SMC0_BR
SMC0 Bus Request Not Muxed SMC0_BR
SMC0_D00 SMC0 Data 0 Not Muxed SMC0_D00
SMC0_D01 SMC0 Data 1 Not Muxed SMC0_D01
SMC0_D02 SMC0 Data 2 Not Muxed SMC0_D02
SMC0_D03 SMC0 Data 3 Not Muxed SMC0_D03
SMC0_D04 SMC0 Data 4 Not Muxed SMC0_D04
SMC0_D05 SMC0 Data 5 Not Muxed SMC0_D05
SMC0_D06 SMC0 Data 6 Not Muxed SMC0_D06
SMC0_D07 SMC0 Data 7 Not Muxed SMC0_D07
SMC0_D08 SMC0 Data 8 Not Muxed SMC0_D08
SMC0_D09 SMC0 Data 9 Not Muxed SMC0_D09
SMC0_D10 SMC0 Data 10 Not Muxed SMC0_D10
SMC0_D11 SMC0 Data 11 Not Muxed SMC0_D11
SMC0_D12 SMC0 Data 12 Not Muxed SMC0_D12
SMC0_D13 SMC0 Data 13 Not Muxed SMC0_D13
SMC0_D14 SMC0 Data 14 Not Muxed SMC0_D14
SMC0_D15 SMC0 Data 15 Not Muxed SMC0_D15
SMC0_NORCLK SMC0 NOR Clock B PB_00
SMC0_NORDV SMC0 NOR Data Valid Not Muxed SMC0_AOE
_NORDV
SMC0_NORWT SMC0 NOR Wait Not Muxed SMC0_ARDY_NORWT
SPI0_CLK SPI0 Clock D PD_04
SPI0_D2 SPI0 Data 2 D PD_00
SPI0_D3 SPI0 Data 3 D PD_01
SPI0_MISO SPI0 Master In, Slave Out D PD_02
SPI0_MOSI SPI0 Master Out, Slave In D PD_03
SPI0_RDY SPI0 Ready D PD_10
SPI0_SEL1
SPI0 Slave Select Output 1 D PD_11
SPI0_SEL2
SPI0 Slave Select Output 2 D PD_01
SPI0_SEL3
SPI0 Slave Select Output 3 D PD_00
SPI0_SEL4
SPI0 Slave Select Output 4 C PC_15
SPI0_SEL5
SPI0 Slave Select Output 5 D PD_09
SPI0_SEL6
SPI0 Slave Select Output 6 C PC_13
SPI0_SEL7
SPI0 Slave Select Output 7 C PC_12
SPI0_SS
SPI0 Slave Select Input D PD_11
Table 7. ADSP-BF60x 349-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name Description Port Pin Name