Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 28 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
PWM1_AH PWM1 Channel A High Side G PG_03
PWM1_AL PWM1 Channel A Low Side G PG_02
PWM1_BH PWM1 Channel B High Side G PG_00
PWM1_BL PWM1 Channel B Low Side E PE_15
PWM1_CH PWM1 Channel C High Side E PE_13
PWM1_CL PWM1 Channel C Low Side E PE_12
PWM1_DH PWM1 Channel D High Side E PE_11
PWM1_DL PWM1 Channel D Low Side E PE_10
PWM1_SYNC PWM1 Sync G PG_05
PWM1_TRIP0
PWM1 Shutdown Input 0 G PG_06
PWM1_TRIP1
PWM1 Shutdown Input 1 G PG_08
RSI0_CLK RSI0 Clock G PG_06
RSI0_CMD RSI0 Command G PG_05
RSI0_D0 RSI0 Data 0 G PG_03
RSI0_D1 RSI0 Data 1 G PG_02
RSI0_D2 RSI0 Data 2 G PG_00
RSI0_D3 RSI0 Data 3 E PE_15
RSI0_D4 RSI0 Data 4 E PE_13
RSI0_D5 RSI0 Data 5 E PE_12
RSI0_D6 RSI0 Data 6 E PE_10
RSI0_D7 RSI0 Data 7 E PE_11
SMC0_A01 SMC0 Address 1 Not Muxed SMC0_A01
SMC0_A02 SMC0 Address 2 Not Muxed SMC0_A02
SMC0_A03 SMC0 Address 3 A PA_00
SMC0_A04 SMC0 Address 4 A PA_01
SMC0_A05 SMC0 Address 5 A PA_02
SMC0_A06 SMC0 Address 6 A PA_03
SMC0_A07 SMC0 Address 7 A PA_04
SMC0_A08 SMC0 Address 8 A PA_05
SMC0_A09 SMC0 Address 9 A PA_06
SMC0_A10 SMC0 Address 10 A PA_07
SMC0_A11 SMC0 Address 11 A PA_08
SMC0_A12 SMC0 Address 12 A PA_09
SMC0_A13 SMC0 Address 13 B PB_02
SMC0_A14 SMC0 Address 14 A PA_10
SMC0_A15 SMC0 Address 15 A PA_11
SMC0_A16 SMC0 Address 16 B PB_03
SMC0_A17 SMC0 Address 17 A PA_12
SMC0_A18 SMC0 Address 18 A PA_13
SMC0_A19 SMC0 Address 19 A PA_14
SMC0_A20 SMC0 Address 20 A PA_15
SMC0_A21 SMC0 Address 21 B PB_06
SMC0_A22 SMC0 Address 22 B PB_07
SMC0_A23 SMC0 Address 23 B PB_08
SMC0_A24 SMC0 Address 24 B PB_10
SMC0_A25 SMC0 Address 25 B PB_11
Table 7. ADSP-BF60x 349-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name Description Port Pin Name