Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 27 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
PPI1_D08 EPPI1 Data 8 C PC_08
PPI1_D09 EPPI1 Data 9 C PC_09
PPI1_D10 EPPI1 Data 10 C PC_10
PPI1_D11 EPPI1 Data 11 C PC_11
PPI1_D12 EPPI1 Data 12 C PC_12
PPI1_D13 EPPI1 Data 13 C PC_13
PPI1_D14 EPPI1 Data 14 C PC_14
PPI1_D15 EPPI1 Data 15 C PC_15
PPI1_D16 EPPI1 Data 16 D PD_00
PPI1_D17 EPPI1 Data 17 D PD_01
PPI1_FS1 EPPI1 Frame Sync 1 (HSYNC) B PB_13
PPI1_FS2 EPPI1 Frame Sync 2 (VSYNC) D PD_06
PPI1_FS3 EPPI1 Frame Sync 3 (FIELD) B PB_15
PPI2_CLK EPPI2 Clock B PB_00
PPI2_D00 EPPI2 Data 0 A PA_00
PPI2_D01 EPPI2 Data 1 A PA_01
PPI2_D02 EPPI2 Data 2 A PA_02
PPI2_D03 EPPI2 Data 3 A PA_03
PPI2_D04 EPPI2 Data 4 A PA_04
PPI2_D05 EPPI2 Data 5 A PA_05
PPI2_D06 EPPI2 Data 6 A PA_06
PPI2_D07 EPPI2 Data 7 A PA_07
PPI2_D08 EPPI2 Data 8 A PA_08
PPI2_D09 EPPI2 Data 9 A PA_09
PPI2_D10 EPPI2 Data 10 A PA_10
PPI2_D11 EPPI2 Data 11 A PA_11
PPI2_D12 EPPI2 Data 12 A PA_12
PPI2_D13 EPPI2 Data 13 A PA_13
PPI2_D14 EPPI2 Data 14 A PA_14
PPI2_D15 EPPI2 Data 15 A PA_15
PPI2_D16 EPPI2 Data 16 B PB_07
PPI2_D17 EPPI2 Data 17 B PB_08
PPI2_FS1 EPPI2 Frame Sync 1 (HSYNC) B PB_01
PPI2_FS2 EPPI2 Frame Sync 2 (VSYNC) B PB_02
PPI2_FS3 EPPI2 Frame Sync 3 (FIELD) B PB_03
PWM0_AH PWM0 Channel A High Side F PF_01
PWM0_AL PWM0 Channel A Low Side F PF_00
PWM0_BH PWM0 Channel B High Side F PF_03
PWM0_BL PWM0 Channel B Low Side F PF_02
PWM0_CH PWM0 Channel C High Side F PF_05
PWM0_CL PWM0 Channel C Low Side F PF_04
PWM0_DH PWM0 Channel D High Side F PF_07
PWM0_DL PWM0 Channel D Low Side F PF_06
PWM0_SYNC PWM0 Sync E PE_08
PWM0_TRIP0
PWM0 Shutdown Input 0 E PE_09
PWM0_TRIP1
PWM0 Shutdown Input 1 F PF_11
Table 7. ADSP-BF60x 349-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name Description Port Pin Name