Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 26 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
LP3_D6 LP3 Data 6 F PF_14
LP3_D7 LP3 Data 7 F PF_15
PA_00 – PA_15 PORTA Position 00 through PORTA Position 15 A PA_00 – PA_15
PB_00 – PB_15 PORTB Position 00 through PORTB Position 15 B PB_00 – PB_15
PC_00 – PC_15 PORTC Position 00 through PORTC Position 15 C PC_00 – PC_15
PD_00 – PD_15 PORTD Position 00 through PORTD Position 15 D PD_00 – PD_15
PE_00 – PE_15 PORTE Position 00 through PORTE Position 15 E PE_00 – PE_15
PF_00 – PF_15 PORTF Position 00 through PORTF Position 15 F PF_00 – PF_15
PG_00 – PG_15 PORTG Position 00 through PORTG Position 15 G PG_00 – PG_15
PPI0_CLK EPPI0 Clock E PE_09
PPI0_D00 EPPI0 Data 0 F PF_00
PPI0_D01 EPPI0 Data 1 F PF_01
PPI0_D02 EPPI0 Data 2 F PF_02
PPI0_D03 EPPI0 Data 3 F PF_03
PPI0_D04 EPPI0 Data 4 F PF_04
PPI0_D05 EPPI0 Data 5 F PF_05
PPI0_D06 EPPI0 Data 6 F PF_06
PPI0_D07 EPPI0 Data 7 F PF_07
PPI0_D08 EPPI0 Data 8 F PF_08
PPI0_D09 EPPI0 Data 9 F PF_09
PPI0_D10 EPPI0 Data 10 F PF_10
PPI0_D11 EPPI0 Data 11 F PF_11
PPI0_D12 EPPI0 Data 12 F PF_12
PPI0_D13 EPPI0 Data 13 F PF_13
PPI0_D14 EPPI0 Data 14 F PF_14
PPI0_D15 EPPI0 Data 15 F PF_15
PPI0_D16 EPPI0 Data 16 E PE_03
PPI0_D17 EPPI0 Data 17 E PE_04
PPI0_D18 EPPI0 Data 18 E PE_00
PPI0_D19 EPPI0 Data 19 E PE_01
PPI0_D20 EPPI0 Data 20 D PD_12
PPI0_D21 EPPI0 Data 21 D PD_15
PPI0_D22 EPPI0 Data 22 E PE_02
PPI0_D23 EPPI0 Data 23 E PE_05
PPI0_FS1 EPPI0 Frame Sync 1 (HSYNC) E PE_08
PPI0_FS2 EPPI0 Frame Sync 2 (VSYNC) E PE_07
PPI0_FS3 EPPI0 Frame Sync 3 (FIELD) E PE_06
PPI1_CLK EPPI1 Clock B PB_14
PPI1_D00 EPPI1 Data 0 C PC_00
PPI1_D01 EPPI1 Data 1 C PC_01
PPI1_D02 EPPI1 Data 2 C PC_02
PPI1_D03 EPPI1 Data 3 C PC_03
PPI1_D04 EPPI1 Data 4 C PC_04
PPI1_D05 EPPI1 Data 5 C PC_05
PPI1_D06 EPPI1 Data 6 C PC_06
PPI1_D07 EPPI1 Data 7 C PC_07
Table 7. ADSP-BF60x 349-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name Description Port Pin Name