Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 25 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
ETH_PTPCLKIN EMAC0/EMAC1 PTP Clock Input C PC_13
GND Ground Not Muxed GND
JTG_EMU Emulation Output Not Muxed JTG_EMU
JTG_TCK JTAG Clock Not Muxed JTG_TCK
JTG_TDI JTAG Serial Data Input Not Muxed JTG_TDI
JTG_TDO JTAG Serial Data Output Not Muxed JTG_TDO
JTG_TMS JTAG Mode Select Not Muxed JTG_TMS
JTG_TRST
JTAG Reset Not Muxed JTG_TRST
LP0_ACK LP0 Acknowledge B PB_01
LP0_CLK LP0 Clock B PB_00
LP0_D0 LP0 Data 0 A PA_00
LP0_D1 LP0 Data 1 A PA_01
LP0_D2 LP0 Data 2 A PA_02
LP0_D3 LP0 Data 3 A PA_03
LP0_D4 LP0 Data 4 A PA_04
LP0_D5 LP0 Data 5 A PA_05
LP0_D6 LP0 Data 6 A PA_06
LP0_D7 LP0 Data 7 A PA_07
LP1_ACK LP1 Acknowledge B PB_02
LP1_CLK LP1 Clock B PB_03
LP1_D0 LP1 Data 0 A PA_08
LP1_D1 LP1 Data 1 A PA_09
LP1_D2 LP1 Data 2 A PA_10
LP1_D3 LP1 Data 3 A PA_11
LP1_D4 LP1 Data 4 A PA_12
LP1_D5 LP1 Data 5 A PA_13
LP1_D6 LP1 Data 6 A PA_14
LP1_D7 LP1 Data 7 A PA_15
LP2_ACK LP2 Acknowledge E PE_08
LP2_CLK LP2 Clock E PE_09
LP2_D0 LP2 Data 0 F PF_00
LP2_D1 LP2 Data 1 F PF_01
LP2_D2 LP2 Data 2 F PF_02
LP2_D3 LP2 Data 3 F PF_03
LP2_D4 LP2 Data 4 F PF_04
LP2_D5 LP2 Data 5 F PF_05
LP2_D6 LP2 Data 6 F PF_06
LP2_D7 LP2 Data 7 F PF_07
LP3_ACK LP3 Acknowledge E PE_07
LP3_CLK LP3 Clock E PE_06
LP3_D0 LP3 Data 0 F PF_08
LP3_D1 LP3 Data 1 F PF_09
LP3_D2 LP3 Data 2 F PF_10
LP3_D3 LP3 Data 3 F PF_11
LP3_D4 LP3 Data 4 F PF_12
LP3_D5 LP3 Data 5 F PF_13
Table 7. ADSP-BF60x 349-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name Description Port Pin Name