Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 22 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
SPT_BD1 I/O Channel B Data 1 Secondary bidirectional data I/O. This signal can be configured as an output to
transmit serial data, or as an input to receive serial data.
SPT_BFS I/O Channel B Frame Sync The frame sync pulse initiates shifting of serial data. This signal is either
generated internally or externally.
SPT_BTDV Output Channel B Transmit Data Valid This signal is optional and only active when SPORT is configured in
multi-channel transmit mode. It is asserted during enabled slots.
SYS_BMODEn Input Boot Mode Control n Selects the boot mode of the processor.
SYS_CLKIN Input Clock/Crystal Input Connect to an external clock source or crystal.
SYS_CLKOUT Output Processor Clock Output Outputs internal clocks. Clocks may be divided down. See the CGU chapter in
the processor hardware reference for more details.
SYS_EXTWAKE Output External Wake Control Drives low during hibernate and high all other times. Typically connected to the
enable input of the voltage regulator controlling the V
DD_INT
supply.
SYS_FAULT
I/O Complementary Fault Complement of SYS_FAULT.
SYS_FAULT I/O Fault Indicates internal faults or senses external faults depending on the operating mode.
SYS_HWRST
Input Processor Hardware Reset Control Resets the device when asserted.
SYS_IDLEn
Output Core n Idle Indicator When low indicates that core n is in idle mode or being held in reset.
SYS_NMI
Input Non-maskable Interrupt Priority depends on the core that receives the interrupt. See the processor
hardware and programming references for more details.
SYS_PWRGD Input Power Good Indicator When high it indicates to the processor that the V
DD_INT
level is within specifica-
tions such that it is safe to begin booting upon return from hibernate.
SYS_RESOUT
Output Reset Output Indicates that the device is in the reset state.
SYS_SLEEP
Output Processor Sleep Indicator When low indicates that the processor is in the deep sleep power saving
mode.
SYS_TDA Input Thermal Diode Anode May be used by an external temperature sensor to measure the die temperature.
SYS_TDK Input Thermal Diode Cathode May be used by an external temperature sensor to measure the die
temperature.
SYS_XTAL Output Crystal Output Drives an external crystal. Must be left unconnected if an external clock is driving CLKIN.
TMR_ACIn Input Alternate Capture Input n Provides an additional input for WIDCAP, WATCHDOG, and PININT modes.
TMR_ACLKn Input Alternate Clock n Provides an additional time base for use by an individual timer.
TMR_CLK Input Clock Provides an additional global time base for use by all the GP timers.
TMR_TMRn I/O Timer n The main input/output signal for each timer.
TWI_SCL I/O Serial Clock Clock output when master, clock input when slave.
TWI_SDA I/O Serial Data Receives or transmits data.
UART_CTS
Input Clear to Send Flow control signal.
UART_RTS
Output Request to Send Flow control signal.
UART_RX
Input Receive Receive input. Typically connects to a transceiver that meets the electrical requirements of the
device being communicated with.
UART_TX
Output Transmit Transmit output. Typically connects to a transceiver that meets the electrical requirements of
the device being communicated with.
USB_CLKIN Input Clock/Crystal Input This clock input is multiplied by a PLL to form the USB clock. See Universal Serial
Bus (USB) On-The-Go—Receive and Transmit Timing for frequency/tolerance information.
USB_DM I/O Data – Bidirectional differential data line.
USB_DP I/O Data + Bidirectional differential data line.
USB_ID Input OTG ID Senses whether the controller is a host or device. This signal is pulled low when an A-type plug
is sensed (signifying that the USB controller is the A device), but the input is high when a B-type plug is
sensed (signifying that the USB controller is the B device).
USB_VBC Output VBUS Control Controls an external voltage source to supply VBUS when in host mode. May be
configured as open drain. Polarity is configurable as well.
USB_VBUS I/O Bus Voltage Connects to bus voltage in host and device modes.
Table 6. Detailed Signal Descriptions (Continued)
Signal Name Direction Description