Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 19 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
ADSP-BF60x DETAILED SIGNAL DESCRIPTIONS
Table 6 provides a detailed description of each signal.
Table 6. Detailed Signal Descriptions
Signal Name Direction Description
ACM_An Output ADC Control Signals Function varies by mode.
ACM_CLK Output Clock SCLK derived clock for connecting to an ADC.
ACM_FS Output Frame Sync Typically used as an ADC chip select.
ACM_Tn Input External Trigger n Input for external trigger events.
CAN_RX Input Receive Typically an external CAN transceiver's RX output.
CAN_TX Output Transmit Typically an external CAN transceiver's TX input.
CNT_DG Input Count Down and Gate Depending on the mode of operation this input acts either as a count down
signal or a gate signal.
Count Down: This input causes the GP counter to decrement.
Gate: Stops the GP counter from incrementing or decrementing.
CNT_UD Input Count Up and Direction Depending on the mode of operation this input acts either as a count up signal
or a direction signal.
Count Up: This input causes the GP counter to increment.
Direction: Selects whether the GP counter is incrementing or decrementing.
CNT_ZM Input Count Zero Marker Input that connects to the zero marker output of a rotary device or detects the
pressing of a push button.
DMC_Ann Output Address n Address bus.
DMC_BAn Output Bank Address Input n Defines which internal bank an ACTIVATE, READ, WRITE, or PRECHARGE command
is being applied to on the dynamic memory. Also defines which mode registers (MR, EMR, EMR2, and/or
EMR3) are loaded during the LOAD MODE REGISTER command.
DMC_CAS
Output Column Address Strobe Defines the operation for external dynamic memory to perform in conjunction
with other DMC command signals. Connect to the CAS input of dynamic memory.
DMC_CK
Output Clock (complement) Complement of DMC_CK.
DMC_CK Output Clock Outputs DCLK to external dynamic memory.
DMC_CKE Output Clock enable Active high clock enables. Connects to the dynamic memory’s CKE input.
DMC_CSn
Output Chip Select n Commands are recognized by the memory only when this signal is asserted.
DMC_DQnn I/O Data n Bidirectional data bus.
DMC_LDM Output Data Mask for Lower Byte Mask for DMC_DQ07:DMC_DQ00 write data when driven high. Sampled on
both edges of the data strobe by the dynamic memory.
DMC_LDQS
I/O Data Strobe for Lower Byte (complement) Complement of LDQS. Not used in single-ended mode.
DMC_LDQS I/O Data Strobe for Lower Byte DMC_DQ07:DMC_DQ00 data strobe. Output with Write Data. Input with
Read Data. May be single-ended or differential depending on register settings.
DMC_ODT Output On-die Termination Enables dynamic memory termination resistances when driven high (assuming
the memory is properly configured). ODT is enabled/disabled regardless of read or write commands.
DMC_RAS
Output Row Address Strobe Defines the operation for external dynamic memory to perform in conjunction
with other DMC command signals. Connect to the RAS input of dynamic memory.
DMC_UDM Output Data Mask for Upper Byte Mask for DMC_DQ15:DMC_DQ08 write data when driven high. Sampled on
both edges of the data strobe by the dynamic memory.
DMC_UDQS
I/O Data Strobe for Upper Byte (complement) Complement of UDQS. Not used in single-ended mode.
DMC_UDQS I/O Data Strobe for Upper Byte DMC_DQ15:DMC_DQ08 data strobe. Output with Write Data. Input with
Read Data. May be single-ended or differential depending on register settings.
DMC_WE
Output Write Enable Defines the operation for external dynamic memory to perform in conjunction with other
DMC command signals. Connect to the WE
input of dynamic memory.