Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 16 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Power Management
As shown in Table 4, the processor supports five different power
domains, which maximizes flexibility while maintaining com-
pliance with industry standards and conventions. There are no
sequencing requirements for the various power domains, but all
domains must be powered according to the appropriate Specifi-
cations table for processor operating conditions; even if the
feature/peripheral is not used.
The dynamic power management feature of the processor
allows the processor’s core clock frequency (f
CCLK
) to be dynam-
ically controlled.
The power dissipated by a processor is largely a function of its
clock frequency and the square of the operating voltage. For
example, reducing the clock frequency by 25% results in a 25%
reduction in dynamic power dissipation.
Full-On Operating Mode—Maximum Performance
In the full-on mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the power-up default execution state in which maximum per-
formance can be achieved. The processor cores and all enabled
peripherals run at full speed.
Active Operating Mode—Moderate Dynamic Power Savings
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clocks and system clocks
run at the input clock (SYS_CLKIN) frequency. DMA access is
available to appropriately configured L1 memories.
For more information about PLL controls, see the “Dynamic
Power Management” chapter in the ADSP-BF60x Blackfin Pro-
cessor Hardware Reference.
See Table 5 for a summary of the power settings for each mode.
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
The deep sleep mode maximizes dynamic power savings by dis-
abling the clocks to the processor core and to all synchronous
peripherals. Asynchronous peripherals may still be running but
cannot access internal resources or external memory.
Hibernate State—Maximum Static Power Savings
The hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor cores and to all of the
peripherals. This setting signals the external voltage regulator
supplying the V
DD_INT
pins to shut off using the SYS_
EXTWAKE signal, which provides the lowest static power dissi-
pation. Any critical information stored internally (for example,
memory contents, register contents, and other information)
must be written to a non-volatile storage device prior to remov-
ing power if the processor state is to be preserved.
Since the V
DD_EXT
pins can still be supplied in this mode, all of
the external pins three-state, unless otherwise specified. This
allows other devices that may be connected to the processor to
still have power applied without drawing unwanted current.
Reset Control Unit
Reset is the initial state of the whole processor or one of the
cores and is the result of a hardware or software triggered event.
In this state, all control registers are set to their default values
and functional units are idle. Exiting a full system reset starts
with Core-0 only being ready to boot. Exiting a Core-n only
reset starts with this Core-n being ready to boot.
The Reset Control Unit (RCU) controls how all the functional
units enter and exit reset. Differences in functional require-
ments and clocking constraints define how reset signals are
generated. Programs must guarantee that none of the reset
functions puts the system into an undefined state or causes
resources to stall. This is particularly important when only one
of the cores is reset (programs must ensure that there is no
pending system activity involving the core that is being reset).
Table 3. Clock Dividers
Clock Source Divider
CCLK (core clock) By 4
SYSCLK (System clock) By 2
SCLK0 (system clock for PVP, all
peripherals not covered by
SCLK1)
None
SCLK1 (system clock for SPORTS,
SPI, ACM)
None
DCLK (LPDDR/DDR2 clock) By 2
OCLK (output clock) Programmable
CLKBUF None, direct from SYS_CLKIN
Table 4. Power Domains
Power Domain V
DD
Range
All internal logic V
DD_INT
DDR2/LPDDR V
DD_DMC
USB V
DD_USB
Thermal diode V
DD_TD
All other I/O (includes SYS, JTAG, and Ports pins) V
DD_EXT
Table 5. Power Settings
Mode/State PLL
PLL
Bypassed f
CCLK
f
SYSCLK
,
f
DCLK
,
f
SCLK0
,
f
SCLK1
Core
Power
Full On Enabled No Enabled Enabled On
Active Enabled/
Disabled
Yes Enabled Enabled On
Deep Sleep Disabled — Disabled Disabled On
Hibernate Disabled — Disabled Disabled Off