Datasheet

Rev. 0 | Page 14 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
• Support for remote frames.
• Active or passive network support.
• CAN wakeup from hibernation mode (lowest static power
consumption mode).
• Interrupts, including: TX complete, RX complete, error
and global.
An additional crystal is not required to supply the CAN clock, as
the CAN clock is derived from a system clock through a pro-
grammable divider.
10/100 Ethernet MAC
The processor can directly connect to a network by way of an
embedded fast Ethernet media access controller (MAC) that
supports both 10-BaseT (10M bits/sec) and 100-BaseT (100M
bits/sec) operation. The 10/100 Ethernet MAC peripheral on the
processor is fully compliant to the IEEE 802.3-2002 standard
and it provides programmable features designed to minimize
supervision, bus use, or message processing by the rest of the
processor system.
Some standard features are:
• Support and RMII protocols for external PHYs
• Full duplex and half duplex modes
• Media access management (in half-duplex operation)
• Flow control
• Station management: generation of MDC/MDIO frames
for read-write access to PHY registers
Some advanced features are:
• Automatic checksum computation of IP header and IP
payload fields of RX frames
• Independent 32-bit descriptor-driven receive and transmit
DMA channels
• Frame status delivery to memory through DMA, including
frame completion semaphores for efficient buffer queue
management in software
• TX DMA support for separate descriptors for MAC header
and payload to eliminate buffer copy operations
• Convenient frame alignment modes
• 47 MAC management statistics counters with selectable
clear-on-read behavior and programmable interrupts on
half maximum value
• Advanced power management
• Magic packet detection and wakeup frame filtering
• Support for 802.3Q tagged VLAN frames
• Programmable MDC clock rate and preamble suppression
IEEE 1588 Support
The IEEE 1588 standard is a precision clock synchronization
protocol for networked measurement and control systems. The
processor includes hardware support for IEEE 1588 with an
integrated precision time protocol synchronization engine
(PTP_TSYNC). This engine provides hardware assisted time
stamping to improve the accuracy of clock synchronization
between PTP nodes. The main features of the engine are:
• Support for both IEEE 1588-2002 and IEEE 1588-2008 pro-
tocol standards
• Hardware assisted time stamping capable of up to 12.5 ns
resolution
• Lock adjustment
• Automatic detection of IPv4 and IPv6 packets, as well as
PTP messages
• Multiple input clock sources (SCLK0, RMII clock, external
clock)
• Programmable pulse per second (PPS) output
• Auxiliary snapshot to time stamp external events
USB 2.0 On-the-Go Dual-Role Device Controller
The USB 2.0 OTG dual-role device controller provides a low-
cost connectivity solution for the growing adoption of this bus
standard in industrial applications, as well as consumer mobile
devices such as cell phones, digital still cameras, and MP3 play-
ers. The USB 2.0 controller allows these devices to transfer data
using a point-to-point USB connection without the need for a
PC host. The module can operate in a traditional USB periph-
eral-only mode as well as the host mode presented in the On-
the-Go (OTG) supplement to the USB 2.0 specification.
The USB clock (USB_CLKIN) is provided through a dedicated
external crystal or crystal oscillator.
The USB On-the-Go dual-role device controller includes a
Phase Locked Loop with programmable multipliers to generate
the necessary internal clocking frequency for USB.
POWER AND CLOCK MANAGEMENT
The processor provides four operating modes, each with a dif-
ferent performance/power profile. When configured for a 0 V
internal supply voltage (V
DD_INT
), the processor enters the hiber-
nate state. Control of clocking to each of the processor
peripherals also reduces power consumption. See Table 5 for a
summary of the power settings for each mode.
Crystal Oscillator (SYS_XTAL)
The processor can be clocked by an external crystal, (Figure 6) a
sine wave input, or a buffered, shaped clock derived from an
external clock oscillator. If an external clock is used, it should be
a TTL compatible signal and must not be halted, changed, or
operated below the specified frequency during normal opera-
tion. This signal is connected to the processor’s SYS_CLKIN
pin. When an external clock is used, the SYS_XTAL pin must be
left unconnected. Alternatively, because the processor includes
an on-chip oscillator circuit, an external crystal may be used.
For fundamental frequency operation, use the circuit shown in
Figure 6. A parallel-resonant, fundamental frequency, micro-
processor grade crystal is connected across the SYS_CLKIN and
XTAL pins. The on-chip resistance between SYS_CLKIN and
the XTAL pin is in the 500 kΩ range. Further parallel resistors
are typically not recommended.