Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 109 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
AUTOMOTIVE PRODUCTS
Some models are available with controlled manufacturing to
support the quality and reliability requirements of automotive
applications. Note that these automotive models may have spec-
ifications that differ from the commercial models and designers
should review the product specifications section of this data
sheet carefully. Contact your local ADI account representative
for specific product ordering information and to obtain the spe-
cific Automotive Reliability reports for these models.
ORDERING GUIDE
Model Max. Core Clock
Temperature
Range
1
1
Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 52 for the junction temperature
(T
J
) specification which is the only temperature specification.
Package Description
Package
Option
ADSP-BF606KBCZ-4 400 MHz 0°C to +70°C 349-Ball CSP_BGA BC-349-1
ADSP-BF606BBCZ-4 400 MHz –40°C to +85°C 349-Ball CSP_BGA BC-349-1
ADSP-BF607KBCZ-5 500 MHz 0°C to +70°C 349-Ball CSP_BGA BC-349-1
ADSP-BF607BBCZ-5 500 MHz –40°C to +85°C 349-Ball CSP_BGA BC-349-1
ADSP-BF608KBCZ-5 500 MHz 0°C to +70°C 349-Ball CSP_BGA BC-349-1
ADSP-BF608BBCZ-5 500 MHz –40°C to +85°C 349-Ball CSP_BGA BC-349-1
ADSP-BF609KBCZ-5 500 MHz 0°C to +70°C 349-Ball CSP_BGA BC-349-1
ADSP-BF609BBCZ-5 500 MHz –40°C to +85°C 349-Ball CSP_BGA BC-349-1