Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 100 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Capacitive Loading
Output delays and holds are based on standard capacitive loads
of an average of 6 pF on all pins (see Figure 60). V
LOAD
is equal
to (V
DD_EXT
)/2.
The graphs of Figure 61 through Figure 63 show how output
rise and fall times vary with capacitance. The delay and hold
specifications given should be derated by a factor derived from
these figures. The graphs in these figures may not be linear out-
side the ranges shown.
Figure 58. Driver Type D Current (1.8 V V
DD_EXT
)
Figure 59. Driver Type D Current (3.3 V V
DD_EXT
)
– 10
SOURCE CURRENT (mA)
SOURCE VOLTAGE (V)
0 0.5 1.0 1.5 2.0
0
– 20
V
OL
V
DD_EXT
= 1.9V @ – 40
°
C
V
DD_EXT
= 1.8V @ 25
°
C
– 5
V
DD_EXT
= 1.7V @ 125
°
C
– 15
– 40
SOURCE CURRENT (mA)
SOURCE VOLTAGE (V)
0 1.0 2.0 3.0 4.0
0
– 60
V
OL
V
DD_EXT
= 3.465V @ – 40
°
C
V
DD_EXT
= 3.30V @ 25
°
C
– 20
V
DD_EXT
= 3.135V @ 125
°
C
Figure 60. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
Figure 61. Driver Type A Typical Rise and Fall Times (10%-90%) vs. Load
Capacitance (V
DD_EXT
= 1.8 V)
T1
ZO = 50:(impedance)
TD = 4.04 r 1.18 ns
2pF
TESTER PIN ELECTRONICS
50:
0.5pF
70:
400:
45:
4pF
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
V
LOAD
DUT
OUTPUT
50:
LOAD CAPACITANCE (pF)
12
0
14
8
4
2
6
RISE AND FALL TIMES (ns)
10
0 25020050
100
150
16
t
RISE
t
FALL
t
FALL
= 1.8V @ 25
°
C
t
RISE
= 1.8V @ 25
°
C