Blackfin Dual Core Embedded Processor ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 FEATURES MEMORY Dual-core symmetric high-performance Blackfin processor, up to 500 MHz per core Each core contains two 16-bit MACs, two 40-bit ALUs, and a 40-bit barrel shifter RISC-like register and instruction model for ease of programming and compiler-friendly support Advanced debug, trace, and performance monitoring Pipelined Vision Processor provides hardware to process signal and image algorithms used for pre- and co
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 TABLE OF CONTENTS Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Operating Conditions . . . . . . . . .
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 GENERAL DESCRIPTION The processors offer performance up to 500 MHz, as well as low static power consumption. Produced with a low-power and lowvoltage design methodology, they provide world-class power management and performance.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 ADDRESS ARITHMETIC UNIT 32 DA0 32 L3 B3 M3 I2 L2 B2 M2 I1 L1 B1 M1 I0 L0 B0 M0 SP FP P5 DAG1 P4 P3 DAG0 P2 P1 P0 TO MEMORY DA1 I3 32 PREG 32 RAB SD LD1 LD0 32 32 32 ASTAT 32 32 SEQUENCER R7.H R6.H R7.L R6.L R5.H R5.L R4.H R4.L R3.H R3.L R2.H R2.L R1.H R1.L R0.H R0.L 16 ALIGN 16 8 8 8 8 DECODE BARREL SHIFTER 40 40 A0 32 40 40 A1 LOOP BUFFER CONTROL UNIT 32 DATA ARITHMETIC UNIT Figure 2.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 a very small final memory size. The instruction set also provides fully featured multifunction instructions that allow the programmer to use many of the processor core resources in a single instruction. Coupled with many features more often seen on microcontrollers, this instruction set is very efficient when compiling C and C++ source code.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Event Handling The processor provides event handling that supports both nesting and prioritization. Nesting allows multiple event service routines to be active simultaneously. Prioritization ensures that servicing of a higher-priority event takes precedence over servicing of a lower-priority event.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Figure 3. ADSP-BF606 Internal/External Memory Map Rev.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Figure 4. ADSP-BF607/ADSP-BF608/ADSP-BF609 Internal/External Memory Map Rev.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Internal (Core-Accessible) Memory Booting The L1 memory system is the highest-performance memory available to the Blackfin processor cores. The processor has several mechanisms for automatically loading internal and external memory after a reset. The boot mode is defined by the SYS_BMODE input pins dedicated for this purpose. There are two categories of boot modes. In master boot modes, the processor actively loads data from parallel or serial memories.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 • A 32-bit threshold block with 16 thresholds, a histogram, and run-length encoding • Two 32-bit integral blocks that support regular and diagonal integrals • An up- and down-scaling unit with independent scaling ratios for horizontal and vertical components • Input and output formatters for compatibility with many data formats, including Bayer input format The PVP can form a pipe of all the constituent algorithmic modules and is dynamically reconfigurable to form
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Memory Protection The Blackfin cores feature a memory protection concept, which grants data and/or instruction accesses from enabled memory regions only. A supervisor mode vs. user mode programming model supports dynamically varying access rights. Increased flexibility in memory page size options supports a simple method of static memory partitioning.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 being reset by software. The programmer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. Thereafter, the software must reload the counter before it counts to zero from the programmed value. This protects the system from remaining in an unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 A third counter input can provide flexible zero marker support and can alternatively be used to input the push-button signal of thumb wheels. All three pins have a programmable debouncing circuit. Internal signals forwarded to each general-purpose timer enable these timers to measure the intervals between count events. Boundary registers enable auto-zero operation or simple system warning by interrupts when programmable count values are exceeded.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 • Support for remote frames. • Active or passive network support. • CAN wakeup from hibernation mode (lowest static power consumption mode). • Interrupts, including: TX complete, RX complete, error and global. An additional crystal is not required to supply the CAN clock, as the CAN clock is derived from a system clock through a programmable divider.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 BLACKFIN BLACKFIN TO PLL CIRCUITRY TO USB PLL ȍ2 ȍ 5-12 pf1, 2 SYS_CLKIN SYS_XTAL ȍ * FOR OVERTONE OPERATION ONLY: 18 pF* NOTES: 1. CAPACITANCE VALUE SHOWN INCLUDES BOARD PARASITICS 2. VALUES ARE A PRELIMINARY ESTIMATE. 18 pF * Figure 7. External USB Crystal Connection NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 See Table 5 for a summary of the power settings for each mode. Table 3. Clock Dividers Clock Source CCLK (core clock) SYSCLK (System clock) SCLK0 (system clock for PVP, all peripherals not covered by SCLK1) SCLK1 (system clock for SPORTS, SPI, ACM) DCLK (LPDDR/DDR2 clock) OCLK (output clock) CLKBUF Divider By 4 By 2 None Table 5.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 From a system perspective reset is defined by both the reset target and the reset source as described below. Target defined: • Hardware Reset – All functional units are set to their default states without exception. History is lost. • System Reset – All functional units except the RCU are set to their default states. • Core-n only Reset – Affects Core-n only. The system software should guarantee that the core in reset state is not accessed by any bus master.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 CrossCore Embedded Studio or VisualDSP++ installed (sold separately), engineers can develop software for supported EZKITs or any custom system utilizing supported Analog Devices processors. Software Add-Ins for CrossCore Embedded Studio Analog Devices offers software add-ins which seamlessly integrate with CrossCore Embedded Studio to extend its capabilities and reduce development time.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 ADSP-BF60x DETAILED SIGNAL DESCRIPTIONS Table 6 provides a detailed description of each signal. Table 6.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 6.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 6.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 6.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 349-BALL CSP_BGA SIGNAL DESCRIPTIONS The processors' pin definitions are shown in the table. The columns in this table provide the following information: • Signal Name: The Signal Name column in the table includes the Signal Name for every pin. • Description: The Description column in the table provides a verbose (descriptive) name for the signal.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 7.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 7.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 7.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 7.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 7.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 7.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 7.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 7.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 7.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 GP I/O MULTIPLEXING FOR 349-BALL CSP_BGA Table 8 through Table 14 identifies the pin functions that are multiplexed on the general-purpose I/O pins of the 349-ball CSP_BGA package. Table 8.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 10.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 12.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 14.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 ADSP-BF60x DESIGNER QUICK REFERENCE • Reset Drive: The Reset Drive column in the table specifies the active drive on the signal when the processor is in the reset state. The table provides a quick reference summary of pin related information for circuit board design. The columns in this table provide the following information: • Type: The Pin Type column in the table identifies the I/O type or supply type of the pin.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 15.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 15.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 15.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 15.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 15.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 15.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 15.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 15.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 15.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 15.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 15.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 15.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 15.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 15.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 SPECIFICATIONS For information about product specifications please contact your ADI representative. OPERATING CONDITIONS Parameter VDD_INT Internal Supply Voltage Conditions Min Nominal Max Unit CCLK ≤ 500 MHz 1.19 1.25 1.32 V VDD_EXT 1 External Supply Voltage 1.7 1.8 1.9 V VDD_EXT 1 External Supply Voltage 3.13 3.3 3.47 V DDR2/LPDDR Supply Voltage 1.7 1.8 1.9 V USB Supply Voltage 3.13 3.3 3.47 V 3.13 3.3 3.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Clock Related Operating Conditions Table 17 describes the core clock timing requirements. The data presented in the tables applies to all speed grades (found in Automotive Products on Page 109) except where expressly noted. Figure 8 provides a graphical representation of the various clocks and their available divider values. Table 17.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 ELECTRICAL CHARACTERISTICS Parameter VOH1 VOH1 VOH_DDR22 VOH_DDR23 VOH_LPDDR4 VOH_LPDDR5 VOH_LPDDR6 VOH_LPDDR7 VOL8 VOL8 VOL_DDR22 VOL_DDR23 VOL_LPDDR4 VOL_LPDDR5 VOL_LPDDR6 VOL_LPDDR7 IIH9 IIH_PD10 IIL11 IIL_PU12 IIH_USB013 IIL_USB013 IOZH14 IOZH15 IOZL16 IOZL_PU17 IOZH_TWI18 CIN19, 20 CIN_TWI18, 20 CIN_DDR20, 21 IDD_TD IDD_DEEPSLEEP22, 23 Test Conditions Min VDD_EXT = 1.7 V, IOH = –0.5 mA VDD_EXT – 0.40 VDD_EXT = 3.13 V, IOH = –0.5 mA VDD_EXT – 0.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Parameter IDD_IDLE23 VDD_INT Current in Idle IDD_TYP23 VDD_INT Current IDD_HIBERNATE22, 24 Hibernate State Current IDD_HIBERNATE22, 24 Hibernate State Current Without USB IDD_INT23 VDD_INT Current Test Conditions Min fCCLK = 500 MHz ASFC0 = 0.14 (Idle) ASFC1 = 0 (Disabled) fSYSCLK = 250 MHz, fSCLK0/1 = 125 MHz fDCLK = 0 MHz (DDR Disabled) fUSBCLK = 0 MHz (USB Disabled) No PVP or DMA activity TJ = 25°C fCCLK = 500 MHz ASFC0 = 1.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Total Internal Power Dissipation IDDINT_CCLK_DYN (mA) = Table 19 × (ASFC0 + ASFC1) Total power dissipation has two components: The dynamic current of the PVP is determined by selecting the appropriate use case from Table 22. 1. Static, including leakage current (deep sleep) IDDINT_PVP_DYN (mA) = Table 22 2.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 20. Activity Scaling Factors (ASF) IDDINT Power Vector IDD-PEAK IDD-HIGH IDD-FULL-ON-TYP IDD-APP IDD-NOP IDD-IDLE ASF 1.34 1.25 1.00 0.86 0.72 0.14 Table 21. Static Current—IDD_DEEPSLEEP (mA) –40 1.175 1.7 1.200 1.8 Voltage (VDD_INT) 1.225 1.250 1.275 2.2 2.5 2.7 –20 4.0 4.2 4.6 0 8.2 9.0 9.6 10.6 11.5 12.5 13.4 25 18.3 19.8 21.5 23.2 25.3 27.2 29.0 40 29.6 31.7 34.4 36.8 40.0 42.8 45.4 55 45.4 48.9 52.4 56.4 60.6 65.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 PROCESSOR — ABSOLUTE MAXIMUM RATINGS ESD SENSITIVITY Stresses greater than those listed in Table 23 may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 TIMING SPECIFICATIONS Specifications are subject to change without notice. Clock and Reset Timing Table 26 and Figure 10 describe clock and reset operations. Per the CCLK, SYSCLK, SCLK0, SCLK1, DCLK, and OCLK timing specifications in Table 17 on Page 53, combinations of SYS_CLKIN and clock multipliers must not select clock rates in excess of the processor’s maximum instruction rate. Table 26. Clock and Reset Timing VDD_EXT 1.8 V/3.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Power-Up Reset Timing In Figure 11, VDD_SUPPLIES are VDD_INT, VDD_EXT, VDD_DMC, VDD_USB, and VDD_TD. Table 27. Power-Up Reset Timing Parameter Min Max Unit Timing Requirement tRST_IN_PWR SYS_HWRST Deasserted after VDD_INT, VDD_EXT, VDD_DMC, VDD_USB, VDD_TD, and SYS_ CLKIN are Stable and Within Specification RESET tRST_IN_PWR CLKIN V DD_SUPPLIES Figure 11. Power-Up Reset Timing Rev.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Asynchronous Read Table 28.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Asynchronous Flash Read Table 29. Asynchronous Flash Read Parameter Switching Characteristics tAMSADV SMC0_Ax (Address)/SMC0_AMSx Assertion Before SMC0_NORDV Low1 SMC0_NORDV Active Low Width2 tWADV tDADVARE SMC0_ARE Low Delay From SMC0_NORDV High3 tHARE Output4 Hold After SMC0_ARE High5 6 tWARE SMC0_ARE Active Low Width7 Min VDD_EXT 1.8 V/3.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Asynchronous Page Mode Read Table 30. Asynchronous Page Mode Read VDD_EXT 1.8 V /3.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Synchronous Burst Flash Read Table 31.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Asynchronous Write Table 32. Asynchronous Memory Write (BxMODE = b#00) Parameter Timing Requirement tDARDYAWE1 SMC0_ARDY Valid After SMC0_AWE Low2 Min VDD_EXT 1.8 V/3.3 V Nominal Max (WAT – 2.5) × tSCLK0 – 17.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Asynchronous Flash Write Table 33. Asynchronous Flash Write Parameter Switching Characteristics tAMSADV SMC0_Ax/SMC0_AMSx Assertion Before ADV Low1 tDADVAWE SMC0_AWE Low Delay From ADV High2 tWADV NR_ADV Active Low Width3 tHAWE Output4 Hold After SMC0_AWE High5 6 tWAWE SMC0_AWE Active Low Width7 Min VDD_EXT 1.8 V/3.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Bus Request/Bus Grant Table 35. Bus Request/Bus Grant Parameter Switching Characteristics tDBGBR SMC0_BG Delay After SMC0_BR tENGDAT DATA Enable After SMC0_BG Deassertion tDBGDAT DATA Disable After SMC0_BG Assertion Min VDD_EXT 1.8 V/3.3 V Nominal Max 2.5 × tSCLK0 –3 3.5 × tSCLK0 + 17.5 3 Unit ns ns ns SMC0_BR tDBGBR SMC0_BG tDNGDAT tENGDAT SMC0 DATA/ADDRESS CONTROL Figure 18. Bus Request/Bus Grant DDR2 SDRAM Clock and Control Cycle Timing Table 36.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 DDR2 SDRAM Read Cycle Timing Table 37. DDR2 SDRAM Read Cycle Timing, VDD_DMC Nominal 1.8 V Parameter Timing Requirements tDV tDQSQ tQH tRPRE tRPST 1 Min Data Valid Window DMC0_DQS-DMC0_DQ Skew for DMC0_DQS and Associated DMC0_ DQ Signals DMC0_DQ, DMC0_DQS Output Hold Time From DMC0_DQS Read Preamble Read Postamble In order to ensure proper operation of the DDR2, all the DDR2 guidelines have to be strictly followed.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 DDR2 SDRAM Write Cycle Timing Table 38. DDR2 SDRAM Write Cycle Timing, VDD_DMC Nominal 1.8 V Parameter Switching Characteristics tDQSS2 DMC0_DQS Latching Rising Transitions to Associated Clock Edges tDS tDH tDSS tDSH tDQSH tDQSL tWPRE tWPST tIPW tDIPW 1 2 Min 250 MHz1 Max –0.15 0.15 0.3 0.25 0.25 0.35 0.35 0.35 0.4 0.6 0.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Mobile DDR SDRAM Clock and Control Cycle Timing Table 39. Mobile DDR SDRAM Read Cycle Timing, VDD_DMC Nominal 1.8 V Parameter Switching Characteristics tCK Clock Cycle Time (CL = 2 Not Supported) tCH Minimum Clock Pulse Width tCL Maximum Clock Pulse Width tIS Control/Address Setup Relative to DMC0_CK Rise tIH Control/Address Hold Relative to DMC0_CK Rise 200 MHz Max Min 5 0.45 0.45 1 1 tCK Unit ns tCK tCK ns ns 0.55 0.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Mobile DDR SDRAM Write Cycle Timing Table 41. Mobile DDR SDRAM Write Cycle Timing, VDD_DMC Nominal 1.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Enhanced Parallel Peripheral Interface Timing Table 42 and Figure 25 on Page 72, Figure 27 on Page 74, Figure 26 on Page 73, and Figure 28 on Page 74 describe enhanced parallel peripheral interface timing operations. Table 42.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 FRAME SYNC DRIVEN DATA DRIVEN tPCLK EPPI_CLK tDFSPI tPCLKW tHOFSPI EPPI_FS1/2 tDDTPI EPPI_D00-23 Figure 26. PPI GP Transmit Mode with Internal Frame Sync Timing Rev.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 43.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Link Ports Calculation of link receiver data setup and hold relative to link clock is required to determine the maximum allowable skew that can be introduced in the transmission path length difference between LP_Dx (data) and LP_CLK. Setup skew is the maximum delay that can be introduced in LP_Dx relative to LP_CLK: (setup skew = tLCLKTWH min – tDLDCH – tSLDCL).
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 45. Link Ports—Transmit Parameter Timing Requirements tSLACH tHLACH Switching Characteristics tDLDCH tHLDCH tLCLKTWL tLCLKTWH tDLACLK VDD_EXT 1.8 V Nominal/3.3 V Nominal Max Min LP_ACK Setup Before LP_CLK Low LP_ACK Hold After LP_CLK Low 2 × tSCLK0 + 10 0 Data Delay After LP_CLK High Data Hold After LP_CLK High LP_CLK Width Low LP_CLK Width High LP_CLK Low Delay After LP_ACK High –1 0.4 × tLCLK 0.4 × tLCLK tSCLK0 + 4 tLCLKTWH tLCLKTWL ns ns 2.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Serial Ports To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) serial clock (SPT_CLK) width. In Figure 31 either the rising edge or the falling edge of SPT_CLK (external or internal) can be used as the active sampling edge. Table 46.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 47.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE DATA RECEIVE—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE tSCLKIW SPT_A/BCLK (SPORT CLOCK) SPT_A/BCLK (SPORT CLOCK) tDFSI tDFSE tSFSI tHOFSI tHFSI tSFSE tHFSE tSDRE tHDRE tHOFSE SPT_A/BFS (FRAME SYNC) SPT_A/BFS (FRAME SYNC) tSDRI tHDRI SPT_A/BDx (DATA CHANNEL A/B) SPT_A/BDx (DATA CHANNEL A/B) DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE DATA TRANSMIT—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE tSCLKIW SAMPLE EDGE tSCLK
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 48. Serial Ports—Enable and Three-State Parameter Switching Characteristics tDDTEN Data Enable from External Transmit SPT_CLK1 Data Disable from External Transmit SPT_CLK1 tDDTTE tDDTIN Data Enable from Internal Transmit SPT_CLK1 tDDTTI Data Disable from Internal Transmit SPT_CLK1 1 Min VDD_EXT 1.8 V Nominal Max 1 VDD_EXT 3.3 V Nominal Min Max 1 18.8 –1 14 –1 2.8 2.8 Referenced to drive edge.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 The SPT_TDV output signal becomes active in SPORT multichannel mode. During transmit slots (enabled with active channel selection registers) the SPT_TDV is asserted for communication with external devices. Table 49. Serial Ports—TDV (Transmit Data Valid) VDD_EXT 1.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 50. Serial Ports—External Late Frame Sync VDD_EXT 1.8 V Nominal Min Max Parameter Switching Characteristics tDDTLFSE Data Delay from Late External Transmit Frame Sync or External Receive Frame Sync with MCE = 1, MFD = 01 tDDTENFS Data Enable for MCE = 1, MFD = 01 0.5 1 VDD_EXT 3.3 V Nominal Min 18.8 0.5 The tDDTLFSE and tDDTENFS parameters apply to left-justified as well as standard serial mode, and MCE = 1, MFD = 0.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Serial Peripheral Interface (SPI) Port—Master Timing Table 51 and Figure 35 describe SPI port master operations. Note that: • In dual mode data transmit the SPI_MISO signal is also an output. • In dual mode data receive the SPI_MOSI signal is also an input. • In quad mode data receive the SPI_MOSI, SPI_D2, and SPI_D3 signals are also inputs. • In quad mode data transmit the SPI_MISO, SPI_D2, and SPI_D3 signals are also outputs. Table 51.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 SPI_SEL (OUTPUT) tSDSCIM tSPICLM tSPICHM tSPICLK tHDSM SPI_CLK (OUTPUT) tHDSPIDM tDDSPIDM DATA OUTPUTS (SPI_MOSI) tSSPIDM CPHA = 1 tHSPIDM DATA INPUTS (SPI_MISO) tHDSPIDM tDDSPIDM DATA OUTPUTS (SPI_MOSI) CPHA = 0 tSSPIDM tHSPIDM DATA INPUTS (SPI_MISO) Figure 35. Serial Peripheral Interface (SPI) Port—Master Timing Rev.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Serial Peripheral Interface (SPI) Port—Slave Timing • In dual mode data receive the SPI_MISO signal is also an input. Table 52 and Figure 36 describe SPI port slave operations. Note that: • In quad mode data receive the SPI_MISO, SPI_D2, and SPI_D3 signals are also inputs. • In dual mode data transmit the SPI_MOSI signal is also an output. • In quad mode data transmit the SPI_MOSI, SPI_D2, and SPI_D3 signals are also outputs. Table 52.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 SPI_SS (INPUT) tSDSCI tSPICLS tSPICHS tHDS tSPICLK SPI_CLK (INPUT) tDSOE tDDSPID tDDSPID tHDSPID tDSDHI DATA OUTPUTS (SPI_MISO) CPHA = 1 tSSPID tHSPID DATA INPUTS (SPI_MOSI) tDSOE tHDSPID tDDSPID tDSDHI DATA OUTPUTS (SPI_MISO) CPHA = 0 tHSPID tSSPID DATA INPUTS (SPI_MOSI) Figure 36. Serial Peripheral Interface (SPI) Port—Slave Timing Rev.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing Table 53. SPI Port—SPI_RDY Slave Timing VDD_EXT 1.8 V/3.3 V Nominal Min Max Parameter Switching Characteristics tDSPISCKRDYSR SPI_RDY De-assertion from Valid Input SPI_CLK Edge in Slave Mode Receive 2.5 × tSCLK1 SPI_RDY De-assertion from Valid Input SPI_CLK Edge in Slave Mode Transmit 3.5 × tSCLK1 tDSPISCKRDYST 3.5 × tSCLK1 + 17.5 ns 4.5 × tSCLK1 + 17.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing In Figure 39 and Figure 40, the outputs can be SPI_MOSI SPI_ MISO, SPI_D2, and/or SPI_D3 depending on the mode of operation. Table 54. SPI Port ODM Master Mode Timing Parameter Switching Characteristics tHDSPIODMM SPI_CLK Edge to High Impedance from Data Out Valid SPI_CLK Edge to Data Out Valid from High Impedance tDDSPIODMM Min VDD_EXT 1.8 V/3.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Serial Peripheral Interface (SPI) Port—SPI_RDY Timing Table 56.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 tSRDYSCKM SPI_RDY SPI_CLK (CPOL = 0) SPI_CLK (CPOL = 1) Figure 43. SPI_CLK Switching Diagram after SPI_RDY Assertion, CPHA = x Rev.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 General-Purpose Port Timing Table 57 and Figure 44 describe general-purpose port operations. Table 57. General-Purpose Port Timing Parameter Timing Requirement tWFI General-Purpose Port Pin Input Pulse Width Min VDD_EXT 1.8 V/3.3 V Nominal Max 2 × tSCLK0 Unit ns tWFI GPIO INPUT Figure 44. General-Purpose Port Timing Timer Cycle Timing Table 58 and Figure 45 describe timer expired operations.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Up/Down Counter/Rotary Encoder Timing Table 59. Up/Down Counter/Rotary Encoder Timing VDD_EXT 1.8 V Nominal Parameter Min Max VDD_EXT 3.3 V Nominal Min Max Unit Timing Requirement tWCOUNT Up/Down Counter/Rotary Encoder Input Pulse Width 2 × tSCLK0 2 × tSCLK0 ns CNT_UD CNT_DG CNT_ZM tWCOUNT Figure 46. Up/Down Counter/Rotary Encoder Timing Pulse Width Modulator (PWM) Timing Table 60 and Figure 47 describe PWM operations. Table 60. PWM Timing VDD_EXT 1.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 ADC Controller Module (ACM) Timing Table 61 and Figure 48 describe ACM operations. f SCLK1 f ACLK = -------------------------CKDIV + 1 Note that the ACM clock (ACMx_CLK) frequency in MHz is set by the following equation where CKDIV is a field in the ACM_TC0 register and ranges from 1 to 255. Setup cycles (SC) in Table 61 is also a field in the ACM_TC0 register and ranges from 0 to 4095.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing The UART ports receive and transmit operations are described in the ADSP-BF60x Hardware Reference Manual. CAN Interface The CAN interface timing is described in the ADSP-BF60x Hardware Reference Manual. Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing Table 62 describes the USB On-The-Go receive and transmit operations. Table 62.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 RSI Controller Timing Table 63 and Figure 49 describe RSI controller timing. Table 63. RSI Controller Timing Parameter Timing Requirements Input Setup Time tISU Input Hold Time tIH Switching Characteristics Clock Frequency Data Transfer Mode1 fPP Clock Low Time tWL tWH Clock High Time Clock Rise Time tTLH Clock Fall Time tTHL tODLY Output Delay Time During Data Transfer Mode Output Hold Time tOH 1 Min VDD_EXT 1.8 V Nominal Max 11 2 VDD_EXT 3.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 10/100 Ethernet MAC Controller Timing Table 64 through Table 66 and Figure 50 through Figure 52 describe the 10/100 Ethernet MAC Controller operations. Table 64. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal VDD_EXT 1.8 V/3.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Table 66. 10/100 Ethernet MAC Controller Timing: RMII Station Management VDD_EXT 1.8 V/3.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 JTAG Test And Emulation Port Timing Table 67 and Figure 53 describe JTAG port operations. Table 67. JTAG Port Timing VDD_EXT 1.8 V Nominal Min Parameter Max VDD_EXT 3.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 OUTPUT DRIVE CURRENTS Figure 54 through Figure 59 show typical current-voltage characteristics for the output drivers of the ADSP-BF60x Blackfin processors. The curves represent the current drive capability of the output drivers as a function of output voltage. 100 40 VDD_EXT = 1.9V @ – 40°C VDD_DMC = 1.9V @ – 40°C VDD_EXT = 1.8V @ 25°C VDD_EXT = 1.7V @ 125°C SOURCE CURRENT (mA) SOURCE CURRENT (mA) 20 VOH 0 VOL – 20 80 VDD_DMC = 1.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Capacitive Loading 0 VDD_EXT = 1.9V @ – 40°C Output delays and holds are based on standard capacitive loads of an average of 6 pF on all pins (see Figure 60). VLOAD is equal to (VDD_EXT)/2. VDD_EXT = 1.8V @ 25°C VDD_EXT = 1.7V @ 125°C SOURCE CURRENT (mA) –5 TESTER PIN ELECTRONICS – 10 50: VLOAD T1 VOL DUT OUTPUT 45: 70: – 15 ZO = 50: (impedance) TD = 4.04 r 1.18 ns 50: – 20 0.5pF 4pF 0 0.5 1.0 1.5 2pF 2.0 SOURCE VOLTAGE (V) 400: Figure 58.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 ENVIRONMENTAL CONDITIONS 16 To determine the junction temperature on the application printed circuit board use: 14 RISE AND FALL TIMES (ns) tRISE 12 10 where: 8 TJ = Junction temperature (°C) 6 TCASE = Case temperature (°C) measured by customer at top center of package. 4 JT = From Table 68 2 tFALL = 3.3V @ 25°C tRISE = 3.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Thermal Diode The processor incorporates a thermal diode to monitor the die temperature. The thermal diode is a grounded collector, PNP Bipolar Junction Transistor (BJT). The SYS_TDA ball is connected to the emitter and the SYS_TDK ball is connected to the base of the transistor. These balls can be used by an external temperature sensor (such as the ADM 1021A or the LM86 or others) to read the die temperature of the chip.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 ADSP-BF60x 349-BALL CSP_BGA BALL ASSIGNMENTS The 349-Ball CSP_BGA Ball Assignment (Numerical by Ball Number) table lists the CSP_BGA package by ball number for the ADSP-BF609. The 349-Ball CSP_BGA Ball Assignment (Alphabetical by Pin Name) table lists the CSP_BGA package by signal. 349-BALL CSP_BGA BALL ASSIGNMENT (NUMERICAL BY BALL NUMBER) Ball No.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Ball No.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 349-BALL CSP_BGA BALL ASSIGNMENT (ALPHABETICAL BY PIN NAME) The 349-Ball CSP_BGA Ball Assignment (Numerical by Ball Number) table lists the CSP_BGA package by ball number for the ADSP-BF609.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Pin Name PE_04 PE_05 PE_06 PE_07 PE_08 PE_09 PE_10 PE_11 PE_12 PE_13 PE_14 PE_15 PF_00 PF_01 PF_02 PF_03 PF_04 PF_05 PF_06 PF_07 PF_08 PF_09 PF_10 PF_11 PF_12 PF_13 PF_14 PF_15 PG_00 PG_01 PG_02 PG_03 PG_04 PG_05 PG_06 PG_07 PG_08 PG_09 PG_10 PG_11 PG_12 PG_13 PG_14 PG_15 SMC0_A01 SMC0_A02 SMC0_AMS0 SMC0_AOE_NORDV SMC0_ARDY_NORWT SMC0_ARE Ball No.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 349-BALL CSP_BGA BALL CONFIGURATION Figure 64 shows an overview of signal placement on the 349-ball CSP_BGA package.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 OUTLINE DIMENSIONS Dimensions for the 19 mm 19 mm CSP_BGA package in Figure 65 are shown in millimeters. A1 BALL CORNER 19.10 19.00 SQ 18.90 A1 BALL CORNER 22 20 18 16 14 12 10 8 6 4 2 21 19 17 15 13 11 9 7 5 3 1 A C G 16.80 BSC SQ J F H K L M N 0.80 BSC B D E P R T U W AA TOP VIEW 1.50 1.36 1.21 1.10 REF V Y AB BOTTOM VIEW DETAIL A DETAIL A 1.11 1.01 0.91 0.35 NOM 0.30 MIN SEATING PLANE 0.50 COPLANARITY 0.20 0.45 0.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 AUTOMOTIVE PRODUCTS Some models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models and designers should review the product specifications section of this data sheet carefully.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Rev.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Rev.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10659-0-6/13(0) Rev.
