Datasheet

Rev. B | Page 38 of 44 | July 2013
ADSP-BF592
The time t
ENA_MEASURED
is the interval from when the reference
signal switches to when the output voltage reaches V
TRIP
(high)
or V
TRIP
(low) and is shown below.
•V
DDEXT
(nominal) = 1.8 V, V
TRIP
(high) is 1.05 V, V
TRIP
(low) is 0.75 V
•V
DDEXT
(nominal) = 2.5 V, V
TRIP
(high) is 1.5 V, V
TRIP
(low)
is 1.0 V
•V
DDEXT
(nominal) = 3.3 V, V
TRIP
(high) is 1.9 V, V
TRIP
(low)
is 1.4 V
Time t
TRIP
is the interval from when the output starts driving to
when the output reaches the V
TRIP
(high) or V
TRIP
(low) trip
voltage.
Time t
ENA
is calculated as shown in the equation:
If multiple pins are enabled, the measurement value is that of
the first lead to start driving.
Output Disable Time Measurement
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The output disable time t
DIS
is the
difference between t
DIS_MEASURED
and t
DECAY
as shown on the left
side of Figure 35.
The time for the voltage on the bus to decay by ΔV is dependent
on the capacitive load C
L
and the load current I
L
. This decay
time can be approximated by the equation:
The time t
DECAY
is calculated with test loads C
L
and I
L
, and with
ΔV equal to 0.25 V for V
DDEXT
(nominal) = 2.5 V/3.3 V and
0.15 V for V
DDEXT
(nominal) = 1.8V.
The time t
DIS_MEASURED
is the interval from when the reference
signal switches to when the output voltage decays ΔV from the
measured output high or output low voltage.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
DECAY
using the equation given above. Choose ΔV
to be the difference between the processor’s output voltage and
the input threshold for the device requiring the hold time. C
L
is
the total bus capacitance (per data line), and I
L
is the total leak-
age or three-state current (per data line). The hold time will be
t
DECAY
plus the various output disable times as specified in the
Timing Specifications on Page 22.
Capacitive Loading
Output delays and holds are based on standard capacitive loads
of an average of 6 pF on all pins (see Figure 36). V
LOAD
is equal
to (V
DDEXT
)/2.
The graphs of Figure 37 through Figure 42 show how output
rise time varies with capacitance. The delay and hold specifica-
tions given should be derated by a factor derived from these
figures. The graphs in these figures may not be linear outside the
ranges shown.
t
ENA
t
ENA_MEASURED
t
TRIP
–=
t
DIS
t
DIS_MEASURED
t
DECAY
–=
t
DECAY
C
L
VI
L
=
Figure 36. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
Figure 37. Driver Type A Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (1.8V V
DDEXT
)
T1
ZO = 50:(impedance)
TD = 4.04 r 1.18 ns
2pF
TESTER PIN ELECTRONICS
50:
0.5pF
70:
400:
45:
4pF
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
V
LOAD
DUT
OUTPUT
50:
8
RISE AND FALL TIME (ns)
LOAD CAPACITANCE (pF)
0 50 100 150 250
18
14
0
2
6
12
200
t
RISE
t
FALL
t
FALL
= 1.8V @ 25 ° C
t
RISE
= 1.8V @ 25 ° C
4
10
16
20