Datasheet

ADSP-BF592
Rev. B | Page 35 of 44 | July 2013
JTAG Test And Emulation Port Timing
Table 31 and Figure 24 describe JTAG port operations.
Table 31. JTAG Port Timing
Parameter
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V/3.3V Nominal
Min Max Min Max Unit
Timing Requirements
t
TCK
TCK Period 20 20 ns
t
STAP
TDI, TMS Setup Before TCK High 4 4 ns
t
HTAP
TDI, TMS Hold After TCK High 4 4 ns
t
SSYS
System Inputs Setup Before TCK High
1
45ns
t
HSYS
System Inputs Hold After TCK High
1
55ns
t
TRSTW
TRST Pulse Width
2
(measured in TCK cycles) 4 4 TCK
Switching Characteristics
t
DTDO
TDO Delay from TCK Low 10 10 ns
t
DSYS
System Outputs Delay After TCK Low
3
13 13 ns
1
System inputs = SCL, SDA, PF15–0, PG15–0, PH2–0, TCK, NMI, BMODE3–0, PG.
2
50 MHz maximum.
3
System outputs = CLKOUT, SCL, SDA, PF15–0, PG15–0, PH2–0, TDO, EMU, EXT_WAKE.
Figure 24. JTAG Port Timing
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
t
TCK
t
STAP
t
HTAP
t
DTDO
t
SSYS
t
HSYS
t
DSYS