Datasheet

Rev. B | Page 34 of 44 | July 2013
ADSP-BF592
Timer Cycle Timing
Table 29 and Figure 22 describe timer expired operations. The
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input fre-
quency of (f
SCLK
/2) MHz.
Timer Clock Timing
Table 30 and Figure 23 describe timer clock timing.
Table 29. Timer Cycle Timing
Parameter
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V/3.3V Nominal
Min Max Min Max Unit
Timing Requirements
t
WL
Timer Pulse Width Input Low
(Measured In SCLK Cycles)
1
1 × t
SCLK
1 × t
SCLK
ns
t
WH
Timer Pulse Width Input High
(Measured In SCLK Cycles)
1
1 × t
SCLK
1 × t
SCLK
ns
t
TIS
Timer Input Setup Time Before CLKOUT Low
2
10 8 ns
t
TIH
Timer Input Hold Time After CLKOUT Low
2
–2 –2 ns
Switching Characteristics
t
HTO
Timer Pulse Width Output
(Measured In SCLK Cycles)
1 × t
SCLK
– 2 (2
32
– 1) × t
SCLK
t
SCLK
– 1.5 (2
32
– 1) × t
SCLK
ns
t
TOD
Timer Output Update Delay After CLKOUT High 6 6 ns
1
The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PG0 or PPI_CLK signals in PWM output mode.
2
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.
Figure 22. Timer Cycle Timing
CLKOUT
TMRx OUTPUT
TMRx INPUT
t
TIS
t
TIH
t
WH
,t
WL
t
TOD
t
HTO
Table 30. Timer Clock Timing
Parameter
V
DDEXT
= 1.8 V V
DDEXT
= 2.5V/3.3 V
Min Max Min Max Unit
Switching Characteristic
t
TODP
Timer Output Update Delay After PPI_CLK High 12.64 12.64 ns
Figure 23. Timer Clock Timing
PPI_CLK
TMRx OUTPUT
t
TODP